MPC5604 DSPI TX/RX FIFO queue bytes size?
02-15-2017
02:05 AM
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Zhimin
Contributor I
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Dear Team:
MPC5604 DSPI TX/RX FIFO queue bytes size?
TKS
Best Regards,
Atom
5 Replies
02-15-2017
02:26 AM
1,290 Views
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NXP TechSupport
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Hi,
Which device did you mean?
There is 4-deep TX/RX FIFO on the MPC5604B and 5-deep TX/RX FIFO on the MPC5604P, MPC5604E.
BR, Petr
02-22-2017
11:02 PM
1,290 Views
Zhimin
Contributor I
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hi,jive!
can read PC14 input level when config this pin as SPI1 MISO (my target iic is MPC5604B)?
02-24-2017
02:50 AM
1,290 Views
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NXP TechSupport
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the PC14 cannot be set as SPI1 MISO, did you mean PC4?
For the PC4 if SIU.PCR[36]. IBE bit is set you can read the input level from SIU.GPDI[36] register too.
BR, Petr
02-26-2017
02:57 AM
1,290 Views
Zhimin
Contributor I
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TKS!
02-15-2017
02:29 AM
1,290 Views
Zhimin
Contributor I
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MPC5604B
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