MPC5554 EMIOS programmable input filter implementation question

[ryanbeitlich]

I have a general question on how to implement a EMIOS programmable input filter for the MPC5554.

Using the assumptions:

1. A system clock frequency of 132MHz.

2. GPREN = 0x1, enabling the global clock prescalar.

3. GPRE[7:0] = 0x00000010, setting the global clock prescalar value to 3.

4. UCPREN = 0x1, enabling the unified channel prescalar

5. UCPRE[1:0]= 0x11, setting the clock divider value to 4.

6. FCK=0x0 so is set to prescaled clock.

7. IF=0x1000 (16 clock filter periods).

In the MPC5554 reference manual in figure 17-13 it shows the "Prescaled Clock" input. Is this the same input as the "prescaled clock" output seen in figure 17-54? If it is, then using the Ratio they show in figure 17-54, is (3*4)=12. Would the clock for the EMIOS then be prescaled down by 12, giving a programmed filter time of: 1/(132MHz)*12*16=1.45us?

I ask because my interpretation does not match up clearly to figure 17-12 which has a "internal counter clock" input to the unified prescalar and figure 17-1 which has the "system clock" going to a clock prescalar block.

[PetrS · Accepted solution]

Hi,

The Global Clock Prescaler (MCR[GPRE]) divides the System clock to generate an Internal Counter Clock for the clock prescalers of the unified channels, see Fig 17-1.

This Internal Counter Clock can be further divided by channel Prescaler (CCR[UCPRE]) so channel counts at Prescaler Clock, see Fig 17-12 and Fig 17-54. This Prescaler Clock can be also selected as clock source for programmable input filter.

BR, Petr