Issue with writing to MPC5748G ADC Module

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Issue with writing to MPC5748G ADC Module

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mw98
Contributor II

Hello, 

I am running into an  problem with the ADC module that I am not sure how to diagnose. 

In my application, I am dropping the clock speeds down, along with turning off a lot of modules to get my current draw down to a low level. When I am trying to jump back into the regular speed, I cannot seem to write to the ADC module. I run into an IVOR1 exception. When I try to write to the ADC module with the debugger, I get a purple highlight of the register, indicating that the write did not occur. 

I have looked through the AXI Bus registers and it does not look like any permissions are preventing me from writing to the module. I also do not have the SMPU enabled. 

Are there any status registers that might help me diagnose this issue? Or, is there a simple way to "reset" the modules that I cannot write to?

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petervlna
NXP TechSupport
NXP TechSupport

Hello,

I cannot seem to write to the ADC module. I run into an IVOR1 exception.

Verify that your ADC is correctly clocked before write to it.

38.3.17 Peripheral Status Register 0 (MC_ME_PS0)
This register provides the status of the peripherals.

petervlna_1-1758525193046.png

petervlna_0-1758525167328.png

Other than missing clocks, register protection or XBAR access right I do not see any issues.

But since you will end up in IVOR1 you can track it trough core registers: (see core reference manual)

petervlna_2-1758525331141.png

Best regards,

Peter

 

 

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1,608 Views
petervlna
NXP TechSupport
NXP TechSupport

Hello,

I cannot seem to write to the ADC module. I run into an IVOR1 exception.

Verify that your ADC is correctly clocked before write to it.

38.3.17 Peripheral Status Register 0 (MC_ME_PS0)
This register provides the status of the peripherals.

petervlna_1-1758525193046.png

petervlna_0-1758525167328.png

Other than missing clocks, register protection or XBAR access right I do not see any issues.

But since you will end up in IVOR1 you can track it trough core registers: (see core reference manual)

petervlna_2-1758525331141.png

Best regards,

Peter

 

 

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