Initialization time become longer with D-cache&I-cache enabled 5746C

[ChrisMCU]

hi

for reduced CPU, I've turned D-cahce&I-cache on in startup code, but I find that the initialization become longer than before, is there any operation takes much time when cache is enabled?

Do I have any solution for it?

thanks!

[davidtosenovjan]

Hi, I guess it'll be rather issue with I-cache than D-cache. After POR cache content is invalid, by first code execution the code is being loaded to the cache by bursts, what could cause initial delay (in dependence of the code, with linear code you should see no impact) plus initialization of cache itself (invalidation takes some cycles). On the other hand during runtime having enabled caches greatly increase execution performance.

But if there is some difference in execution time I would not expect much. Do you have some numbers?

You may consider enabling of I-cache in the main application. Another point is whether you are configuring PLL clocks before MCU init, this may significantly increase initialization time.

[ChrisMCU]

Hi,

very appreciate for your reply.

As you said, caches can greatly increase execution performance after been enabled.

that's a good idea to enable cache in the main function, shall D-cache be enabled in main function either?

[davidtosenovjan]

I think in the case of D-cache it shouldn't matter as main portion of data accesses during MCU initialization are SRAM writes (initializing ECC). And these should take same amount of time as on this device used core supports only write-through mode an so SRAM init writes takes same amount of time with cache enabled or disabled.

However still there is a time for D-cache initialization itself (cache invalidation takes 134 CPU cycles).

[ChrisMCU]

I've tried to move this handler to main function, and it works. Thanks a lot.

but I'm still working on why D-cache cannot be enabled in startup code. Finally, I find D-cache may influence flash data readout. when D-cache was enabled, the E-EEPROM data readout time increased a lot.

I will set SMPU to avoid Data consistence, but I don't know which area shall I set, NVM area or SRAM?

[davidtosenovjan]

Please clarify your last sentence, I haven't understand what you want to do. Dont you rather to set cache inhibited attribute for EEPROM address space by CMPU?

[ChrisMCU]

Sorry for my poor English.

Yes, I want to set CI attribute for EEPROM address, but I'm not sure is this right or not.

[davidtosenovjan]

OK, CI attribute is needed to configure by CMPU.

You may use following tool:

https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Core-MPU-configurator/ta-p/1100529