IVOR6 Exception

[latheef]

All,

I am new PowerPC architecture and am working on MPC5775E. I am getting IVOR6 exception with ESR.VLEMI = 1 and ESR.PIL = 1(illegal instruction) but the SRR0 is showing address 0x000000002. I am really not able to figure out what this mean? Please help.

latheef_0-1665868769050.png

[petervlna]

Hello,

Here is the reason why you are getting IVOR6.

7.7.7 Program interrupt (IVOR6)
e200z759n3 implements the Program interrupt as defined by PowerISA 2.06. A program interrupt occurs 
when no higher priority exception exists and one or more of the following exception conditions defined in 
PowerISA 2.06 occur:

•  Illegal Instruction exception

•  Privileged Instruction exception

•  Trap exception

•  Unimplemented Operation exception

e200z7 will invoke an Illegal Instruction program exception on attempted execution of the following instructions:
• Unimplemented instructions
• Instruction from the illegal instruction class
• mtspr and mfspr instructions with an undefined SPR specified
• mtdcr and mfdcr instructions with an undefined DCR specified
e200z7 will invoke a Privileged Instruction program exception on attempted execution of the following instructions when MSR[PR]=1 (user mode):
• A privileged instruction
• mtspr and mfspr instructions that specify a SPRN value with SPRN[5]=1 (even if the SPR is undefined).


e200z7 will invoke an Trap exception on execution of the tw and twi instructions if the trap conditions are met and the exception is not also enabled as a Debug interrupt.
e200z759n3 will invoke an Illegal instruction program exception on attempted execution of the instructions lswi, lswx, stswi, stswx, mfapidi, mfdcrx, mtdcrx, or on any PowerISA 2.06 floating point instruction when MSR FP=1. All other defined or allocated instructions that are not implemented by e200z7 will cause a illegal instruction program exception.

In my opinion you either executing instruction which is not supported (like illegal one) or you are accessing memory which is not available.

SRR0 should be set to the effective address of the excepting instruction.\

Save/Restore Register 0 (SRR0). The SRR0 register is used to save machine state on a 
non-critical interrupt, and contains the address of the instruction at which execution resumes 
when an rfi or se_rfi instruction is executed at the end of a non-critical class interrupt 
handler routine.

If not then simply debug step by step your application and find the instruction where it crashes to see if it is executing properly or accessing some illegal/ not granted access memory.

Best regards,

Peter

[latheef]

@petervlna Thanks for your reply. I configured the CAN using expert processor in S32DS for flexCan2 and I get the exception when I receive the CAN message that too after few reception (not fixed).

I have debugged the code and found it happen when try to return from 

void CAN2_BUF0_IRQHandler(void)
{
FLEXCAN_IRQHandler(2U);
}

latheef_3-1666009439006.png

After execution of the FLEXCAN_IRQHandler(2), the execution of the prologue has to happen  but the lr  now points to address 0x0000002 and it give IVOR6 exception.

latheef_2-1666009375449.png

I stepped through the below assembly instruction

008177be: se_lwz r0,12(r1)
008177c0: se_mtlr r0
008177c2: se_addi r1,8
008177c4: se_blr

After lwz R1 has the RAM address as below:

R1 = 1073751424 (0x40002580)

se_lwz  r0,12(r1) updates the R0 to 2 because of the RAM values as below

latheef_5-1666009893596.png

se_blr then branches to address 2.

Appreciate your help!

Thanks

[petervlna]

Hello,

So you are not able to return from ISR to epilogue? Or you are not able to get into ISR from prologue?

After execution of the FLEXCAN_IRQHandler(2), the execution of the prologue has to happen but the lr now points to address 0x0000002 and it give IVOR6 exception.

I am bit confused. IRQ has no prologue nor epilogue (such has only interrupt to core IVORx)

I will try to summarize it:

1. Your CAN triggers interrupt.

2. IVOR4 is called, and prologue is executed.

3. On the end of prologue the jump to CAN ISR is not executed as the link address is pointing to address 0x2 instead of CAN ISR header. Right?

This seems to me like and interrupt table definition / linker file issue.

Best regards,

Peter

[latheef]

@petervlna The code is autogenerated by S32DS from the sample application for MPC5777C but being tried on MPC5775E. I haven't changed anything from what is autogenerated for MPC5777C. Is there any config change I need to do specific for MPC5775E?

Regards!

[latheef · Accepted solution]

@petervlna I missed to answer your question. In my post I wrongly mentioned prologue. The execution of the ISR FLEXCAN_IRQHandler(2U) happens OK and then tries to
return from the ISR to exceute the epilogue. But its not able to return from the ISR to epilogue instead it goes to address 2.
The 4 assembly code I mentioned is only for returning from the ISR to epilogue.

I found the issue. It is with the flexcan_msgbuff_t recvBuf defined local to the function ie to be in stack. 

Thanks for your time!

[christofer_ft]

Greetings @latheef @petervlna ,

I'm having a similar issue in a MPC5777C. Looking into FLEXCAN_IRQHandler(...) source I couldn't find this line "flexcan_msgbuff_t recvBuf". This was something already patched?

Regards.

Christofer