Footprint and PCB layout guidelines of part LPC54114J256BD64

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Footprint and PCB layout guidelines of part LPC54114J256BD64

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N_com
Contributor I

Hi,

    I plan to use LPC54114J256BD64 (LQFP64 package) in my project and please kindly advise on following questions -

1. For above-mentioned package LQFP64, could please advise if there is any thermal pad (exposed heat spreader) at center location of LPC5411 chipset? It would be great if you can share photo (top and bottom view) of above part.

2. If there is no thermal pad at center location, would it be advisable to place another WLCSP-based chipset underneath LPC54114J256BD64 (LQFP64 package)? In other word, I plan to place LPC54114J256BD64 (LQFP64 package) on PCB top layer and to place another WLCSP-based chipset on PCB bottom layer (directly underneath LPC5411). Any issue with such placement if I have PCB space constraint?

Thank for advice.

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

You can download the schematics of LPC54114-EVK board from the link:

https://www.nxp.com/design/microcontrollers-developer-resources/lpcopen-libraries-and-examples/lpcxp...

 

For the BLE audio board NXH3670, you can download it from the link:

https://www.nxp.com/products/wireless/2-4-ghz-audio-streaming/nxh3670-sdk-board:NXH3670SDK

 

Hope it can help you

BR

Xiangjun Rong

 

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3,663 次查看
xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Kim,

Q1). For above-mentioned package LQFP64, could please advise if there is any thermal pad (exposed heat spreader) at center location of LPC5411 chipset? It would be great if you can share photo (top and bottom view) of above part.

>>>>>As the following LQFP64 package I copied from LPC5411x.pdf, there is not any thermal pad (exposed heat spreader) at center location of LPC5411 chipset.

 

xiangjun_rong_0-1619074496555.png

 

Q2. If there is no thermal pad at center location, would it be advisable to place another WLCSP-based chipset underneath LPC54114J256BD64 (LQFP64 package)? In other word, I plan to place LPC54114J256BD64 (LQFP64 package) on PCB top layer and to place another WLCSP-based chipset on PCB bottom layer (directly underneath LPC5411). Any issue with such placement if I have PCB space constraint?

>>>>I think it is okay to place another WLCSP-based chipset underneath LPC54114J256BD64 (LQFP64 package) if it is easy for layout, generally, the WLCSP-based chipset is of small package and consume little power.

 

Hope it can help you

BR

Xiangjun Rong

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N_com
Contributor I

Hi,

   I've downloaded an application note "AN12568 - LPC54114 USB Dongle with NxH3670". There is a block diagram to describe connection for LPC54114 + NxH3670 SDK board. However, I can't find any schematic inside this AN12568.

  Hence could please provide schematic of above-mentioned reference design?

Thank.

 

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N_com
Contributor I

Hi,

Q1. Refer to chapter 3.1.5 in AN12568, P0.12 is defined as MISO whereas P0.13 is defined as MOSI.

N_com_0-1619589856414.png

However based on Table 4 (page 12) in LPC5411 datasheet, there is different definition for P0.12  (MOSI) & P0.13 (MISO). 

N_com_1-1619590216039.png

Hence, could please advise which one is correct?

Q2. Refer to Table 2 in AN12568,

       a) P0.13 is connected to SW0 (SPI_S_MISO) and P0.12 is connected to SW1 (SPI_S_MOSI). Is it still valid?

      b) is it correct to assume that BLE_SDO refers to I2S_SO (naming definition as defined in Table18 in NxH3670 product datasheet) whereas BLE_SDI refers to I2S_SI (naming definition as defined in Table18 in NxH3670 product datasheet)?

N_com_2-1619591396089.png

Thank.

 

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N_com
Contributor I

Hi,

Q3. Refer to Table 2 in AN12568,

       c) I noticed that PIN P1.7 is belong to Flexcomm Interface 7 whereas PIN P0.5 is belong to Flexcomm Interface 6. Is it acceptable to assign I2S function to different Flexcomm Interface? OR it is better to assign I2S within identical Flexcomm Interface only (such as replace P1.7 with P0.11 if go for FC6 or replace P0.5 with P1.13 if opt for FC7)?

N_com_0-1619595760800.png

Q4. Below is information (Figure 13.3, page 88) extracted from LCP5411x product datasheet. Refer to note (3), it's advisable to tie VDDA and VREFP to VDD and tie VREFN to VSS if ADC is not used.

Hence, could please advise how should I connect VDDA, VREFP and VREFN if I wish to keep option to use ADC in near future?

 

N_com_1-1619603569864.png

Q5. Refer to Figure 36 (page 92) which I have extracted from LPC5411x product datasheet, there is mentioned of USB_VBUS pin. So far I can find two pins (P1.6 and P1.11) with function as USB_VBUS from pin description (chapter 6.2, page 11).

      a) Do I need to connect VBUS to both pins or either of those pins will do?

      b) Could I use a voltage divider to connect USB_VBUS pin to the VBUS if I plan to it as bus-powered device? And would it help to solve issue of 5V tolerance?

N_com_0-1619611356190.png

Q6. In Kinetics KL27, there is a pin PTA4 with alternative function as NMI_b. Could I know which pin(s) will offer identical function as NMI_b in LPC5411x? Also, could you illustrate more about this function NMI_b?

Q7. In page 4 of LPCX5411x_Schematic_B_LPCXpresso54114 board.pdf, there are several boot modes available and P0.4 has been reserved for I2C/SPI boot.

N_com_0-1619615153281.png

However in AN12568 Table 2, P0.4 has been reserved as BLE_SPIS_SSN. So should it be changed to P0.9 or P0.14 (as recommended in UM10914 page 19)?

Q8. In page 4 of LPCX5411x_Schematic_B_LPCXpresso54114 board.pdf, there are 4 decoupling capacitors (C5,C51,C16,C40,C17) reserved and shared for all VDD.

 

N_com_1-1619617336752.png

 

However from note (2) in page 88 (LPC5411x product datasheet), it's recommended to place one set of decoupling cap (0.1uF + 0.01uF) to each VDD pin.

So which one is correct implementation? 

N_com_2-1619617453226.png

 

Thank.

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N_com
Contributor I

Hi,

    I've another question regarding supply voltage for LPC5411x -

Q9. , VDD is limited to 3V to 3.6V only for condition "for USB operation only" based on Table 10 as extracted from LPC5411x product datasheet.

What does "for USB operation only" mean in this case? Could please further illustrate?  

N_com_0-1619689129973.png

Q10. I found out below recommended xtal from BOM lists as prepared for LPCx5411x_schematic_b_LPCXpresso54114 board. However, the package is too large to fit into my board. Any alternative for xtal in smaller package?

N_com_1-1619690939426.png

 

Thank.

 

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Kim,

Regarding the word "for USB operation only", it means if you use USB module, you have to connect the VDD with 3.3V power supply(from 3.0V to 3.6V).

For the crystal device, I think it is okay to use a small package crystal with the same frequency.

Hope it can help you

BR

XiangJun Rong

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N_com
Contributor I

Hi XJ,

   Thank for replies for Q9 & Q10. How's about Q1 - Q8? Please kindly help to clarify too.

Q9. Refer to Figure 2 in AN12568, LPC54114 is connected to USB connector for audio streaming transfer through I2S interface to NxH3670. However, I noticed that 1.8V_KL27 (instead of 3.3V) is supplied to LPC54114 even though LPC54114 is connected to USB connector. 

Could you bplease clarify regarding this issue?

 

N_com_0-1620269430546.png

 

Q10. a. Below is information about selection of crystal that I extracted from LPC5411x product datasheet. I can't find any information regarding CL, RS, and DL. So how I should select a "matching" crystal? 

         b. Also, I noticed that the frequency range for crystal is quite wide of which cover 32.768kHz to 25MHz. Any advise how to select correct crystal frequency? 

 

N_com_1-1620269714820.png

Thank.

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

Q9. Refer to Figure 2 in AN12568, LPC54114 is connected to USB connector for audio streaming transfer through I2S interface to NxH3670. However, I noticed that 1.8V_KL27 (instead of 3.3V) is supplied to LPC54114 even though LPC54114 is connected to USB connector.

Could you bplease clarify regarding this issue?

>>>>>I think you have to follow up the specs in data sheet of LPC54114, connect VDD to 3.3V if you use USB. I am not familiar with  NxH3670, does it require only 1.8V logic?

Q10. a. Below is information about selection of crystal that I extracted from LPC5411x product datasheet. I can't find any information regarding CL, RS, and DL. So how I should select a "matching" crystal?

>>>>The CL,RS and DL are parameters for the crystal, which are from crystal manufacturer. The formula CX1 = CX2 = 2CL -(CPad + CParasitic)  tell you how to compute the CL with external capacitor, pad cap, parasitic cap. The CL is required by crystal manufacturer.

 

b. Also, I noticed that the frequency range for crystal is quite wide of which cover 32.768kHz to 25MHz. Any advise how to select correct crystal frequency?

>>>>There are two external clock, one clock is from PIO0_22 pin, it is called CLKIN, the range can be from 1MHz to 25MHz, but it must be clock source rather than crystal. The PLL can use the CLKIN clock as input clock.

 

>>>>For the RTC crystal(input from RTCXIN and RTCXOUT pins), I think it must be 32.768kHz crystal. The PLL can use the 32.768KHz clock as input clock.

Hope it can help you

BR

XiangJun Rong

 

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

You can download the schematics of LPC54114-EVK board from the link:

https://www.nxp.com/design/microcontrollers-developer-resources/lpcopen-libraries-and-examples/lpcxp...

 

For the BLE audio board NXH3670, you can download it from the link:

https://www.nxp.com/products/wireless/2-4-ghz-audio-streaming/nxh3670-sdk-board:NXH3670SDK

 

Hope it can help you

BR

Xiangjun Rong

 

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