Flush L1 cache on MPC5777M?

[jschloss]

Looking at ch 15.7.91 in the MPC5777M reference manual, I see I can invalidate the data cache by set and way using L1FINV0, but there is not a cache command that lists flush, just invalidate. Can this register flush the cache, or do I have to use dcbf (potentially over all of cache-able memory?) to flush the cache? Also, if I set the L1CSR0.DCWA bit to zero, will all writes be noncache-able?

[davidtosenovjan · Accepted solution]

Hi, Flush All is not supported by this core (as I know no e200 supports this).

Flushing of all cache content would be need needed to do by dcbf sequentially per all lines. However, I am not sure if it does make sense, as the device’s does not have copy-back mode. If there is only writethrough mode, is there any reason for explicit flushing?

If DCWA = 0, then all writes are actually cache inhibited. Cache line will be allocated only during reads.

[jschloss]

I think I thought the cache was a write-back cache, and was trying to make sure memory was consistent if I wanted to turn off the cache before inspecting areas of memory used by DMA. I have some regions non-cachable/guarded with the MPU, but wanted to see if I could get away with turning off the cache in a few cases since I was running low on region descriptors.

If the cache doesn't cache writes, I guess I am fine with just turning it off without losing data.

Ok, so if all writes are write-through, is there any advantage to setting DCWA to 1? Would it allocate that cache line for future reads near (within a cache line) that write, before I start reading? More of an eviction strategy hint?

[davidtosenovjan]

For DCWA=1:
A write allocates cache line what means subsequent read of this data (or the data within this line) may be faster (as stored data are placed to store buffer and written to target memory later).
I cannot tell you which strategy is better, it'll be application dependent enough. Probably if application contains lot of back-to-back access, it could be advantageous.