Hello,
We are working on checking the flash memory array integrity check on MPC5746C.
Based on the steps mentioned in the MPC5746C reference manual we have written the function. When execute this function, continuous reset is happening.

Besed on the steps, below code is written. And it is giving continuous reset in while loop. But if I keep breakpoints and go step by step it is working.
Could you check once and provide your feedback or solution?
static void WaitForAIDBitSet(uint32_t timeout)
{
volatile int delay;
for (delay = 0; delay < 1000; delay++) { __asm__ volatile ("nop"); }
while ((C55FMC.UT0.B.AID == 0) && (timeout > 0U))
{
timeout--;
}
}
uint8 Flash_Memory_Integrity_Test(void)
{
uint32_t misr_result[10];
/* Disable watchdog */
Wdg_modeSwitchInt(FALSE);
/* Step 1: Enter UTest Mode */
C55FMC_UT0 = 0xF9F99999;
/* Step 2: ECC Config - Disable ECC error reporting */
C55FMC.MCR.B.EER = 0; // ECC Event Reporting
C55FMC.MCR.B.SBC = 0; // Single Bit Correction
/* Step 3: Configure PFLASH read behavior */
PFLASH.PFCR1.B.RWSC = 0x04; // Wait States
PFLASH.PFCR1.B.APC = 0x01; // Prefetch Enable
/* Step 4: Select flash blocks to test via SELx */
C55FMC.SEL0.R = 0x00FF0FFC;
C55FMC.SEL1.R = 0x00000000;
C55FMC.SEL2.R = 0x00000000;
C55FMC.SEL3.R = 0x00000000;
/* Step 5: Use sequential addressing */
C55FMC.UT0.B.AIS = 1;
/* Step 6: Seed the MISR registers */
C55FMC_UM0 = MISR_SEED;
C55FMC_UM1 = MISR_SEED;
C55FMC_UM2 = MISR_SEED;
C55FMC_UM3 = MISR_SEED;
C55FMC_UM4 = MISR_SEED;
C55FMC_UM5 = MISR_SEED;
C55FMC_UM6 = MISR_SEED;
C55FMC_UM7 = MISR_SEED;
C55FMC_UM8 = MISR_SEED;
C55FMC_UM9 = MISR_SEED;
/* Step 7: Start Array Integrity Operation */
C55FMC.UT0.B.AIE = 1;
/* Step 8: Wait for AID = 1 (operation complete) */
WaitForAIDBitSet(0xFFFFFF); // Add a timeout limit
/* Step 9: Read back MISR values */
misr_result[0] = C55FMC_UM0;
misr_result[1] = C55FMC_UM1;
misr_result[2] = C55FMC_UM2;
misr_result[3] = C55FMC_UM3;
misr_result[4] = C55FMC_UM4;
misr_result[5] = C55FMC_UM5;
misr_result[6] = C55FMC_UM6;
misr_result[7] = C55FMC_UM7;
misr_result[8] = C55FMC_UM8;
misr_result[9] = C55FMC_UM9;
/* Step 10: Clear AIE */
C55FMC.UT0.B.AIE = 0;
/* Step 11: Enable watchdog back if needed */
Wdg_modeSwitchInt(TRUE);
/* Step 12: Compare MISR results */
if ((misr_result[0] == MISR_UM0) &&
(misr_result[1] == MISR_UM1) &&
(misr_result[2] == MISR_UM2) &&
(misr_result[3] == MISR_UM3) &&
(misr_result[4] == MISR_UM4) &&
(misr_result[5] == MISR_UM5) &&
(misr_result[6] == MISR_UM6) &&
(misr_result[7] == MISR_UM7) &&
(misr_result[8] == MISR_UM8) &&
(misr_result[9] == MISR_UM9))
{
return FLS_SAFE_STATE_INACTIVE;
}
else
{
return FLS_SAFE_STATE_ACTIVE; // Integrity check failed
}
}