DSPI: 64 bits frames?

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DSPI: 64 bits frames?

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EAlepins
Contributor V

Hi,

We are using the DSPI module (in SPI mode) of the MPC5777C. The documentation says in §42.2.2 "Features" that 16 bits is the natural frame size but that with Continuous Selection Format, it is possible to reach 32 bits frames:

   • Programmable serial frame size: 4 to 32
   • SPI frames longer than 16 bits can be supported using the continuous selection format.

I don't see why with the same arguments we couldn't go to 64 bits frames. We'd only have to:

- Push 4 words in the PUSHR (each with 16 bits of data)

- Always use the same CTAR (with 16 bits frame size)

- First 3 words would enable PUSHR[CONT], last word would deassert it

- Make sure the 4 words are pushed in the TX FIFO close to each other so that the DSPI doesn't get an empty TX FIFO between two frames of the whole 64 bits message.

We could even go further than 64 bits (e.g. 80 bits) by polling the TX FIFO and pushing more words to it as soon as one entry is poped...

Will that work? Thanks.

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PetrS
NXP TechSupport
NXP TechSupport

Hi Etienne,

yes, agree.

Petr

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383 Views
PetrS
NXP TechSupport
NXP TechSupport

Hi Etienne,

yes, with the continuous selection format you can have 64bit frame or more, exactly as you wrote.

I guess words in the RM should be

• Programmable serial frame size: 4 to 16

BR, Petr

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karthikkumarnad
Contributor I

Hi Petr,

The data load from FIFO to shift register is a 32 bit parallel bus. So it might take one clock cycle to transfer the data from FIFO to the shift register.

Will this affect the data transfer time?

Is this why the RM says 4 to 32?

Thanks,

Karthik

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EAlepins
Contributor V

Hi,

Thanks. And do you agree we could even do a frame of more than 64 bits by filling the TX FIFO as soon as a frame is sent?

Étienne

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PetrS
NXP TechSupport
NXP TechSupport

Hi Etienne,

yes, agree.

Petr