DMA_MUX trigger source problem

[彭冬冬]

Picture1 show the relationship which PIT you should use when configure the DMA channel in periodic triggering mode 

if i choose the DMA 16  channel , and choose the DMAMUX_1 source 3 , then which PIT channel i should configure as a periodic trigger?

DMAMUX_1.CHCFG[0].R = 0xC3;// enable periodic triggering mode  ,i think PIT channel 0 or 2? 

[martin_kovar]

Hello,

could you please specify microcontroller you use? I need to check reference manual to tell you correct answer.

Regards,

Martin

[彭冬冬]

thank you for your reply!

im using the micrcontroller MPC5744！

Regard，

Colin

[martin_kovar]

Hello Colin,

if you use DMA_MUX in trigger mode, please ignore table 7-18 and 7-19 and see only table 7-17.

As soon as you have configured DMA_MUX in trigger mode, you can select source 0-3. If you select source 0, PIT channel 0 is used to trigger DMA channel and so on.

So, in your case, if you choose source 3, from my point of view PIT channel 3 will be used.

Regards,

Martin

[彭冬冬]

1. perhaps your undersatanding of the  PIT channel is not right,

cos there is no 0 source ,DMAMUX source slot count from 1  from the table 7-19

         0 means DMAMUX channel trigger,  corresponding PIT channel 0

         e.g DMAMUX_1.CHCFG[0].R = 0xC3  this is  0 channel ,should be triggered by PIT 0 ,in desipte of which source you choose.

          but the question is it is still useless when i finished to configure the PIT channel 0 , so im confused? 

2. i wonder if it just transmit Data just once if the DMA is not in triggered mode(normal) ,or is there any ways to trigger the DMA multiple times if i dont use the trigger mode ,or just one way to realize the goal by putting the DMA in triggered mode ? 

3. anyone ever use the multple transmit DMA function, can you give me some advices? 

[martin_kovar]

Hello,

I am sorry for my previous answer. It seems that things are little bit different.

For triggering, only DMA channels 0,1,2 and 3 can be used. So, you can use only DMA_MUX_0 CHCFG0 - CHCFG3. Source must be set to 24 - 29.

DMA channel 0 is connected with PIT channel 0, DMA channel 1 is connected to PIT channel 1 and so on.

I can see my colleague sent you answer in the thread below:

https://community.nxp.com/thread/504935 

Regards,

Martin

[彭冬冬]

can i  ask you another question, if there is any chance , SPI TX buffer is full ,but not be transfered to SPI  shift register ?  im confused, i think ionly if  TX buffer has a data, it can be transfered to SPI shift register automatically.