Correctable single-bit internal RAM Error on MPC5777C

[ashwinkumar]

We are using the MPC5777C controller for one of our project, had a question on internal RAM Single Bit Correction.
We make use of EIM module to inject single bit RAM error (on the 64-bit data bus) and understand the error gets injected when we access the internal RAM.

Does the controller auto updates the physical RAM location with correct data value ?

[petervlna]

Hi,

The controller carries ECC logic. On ECC check it corrects the read data from SRAM and send corrected data further to requesting master.

But it does not correct/physically change data in SRAM array. Indicated fault address is corrupt and user must take care of this data in corrupt location in memory.

Peter

[EAlepins]

This is surprising. Correct me if I am wrong, but with MPC55xx/56xx devices that did not have e2eECC, a single bit error in the RAM was physically corrected by the RAM controller. That means with newer devices, single bit errors occurring at large time intervals accumulate and form multiple bit errors, which are not correctable! Right?

[petervlna]

Hi Etienne,

It is exactly as I have wrote. This is valid for MPC5xxx family.

SRAM controller does not correct physically 1-bit ECC in SRAM array.

1. Corrupted data are read from SRAM

2.ECC mechanism (located at RAM controller) corrects 1bit ECC

3.Corrected data are then sent to requesting master.

4. ECC logic do not physically correct data in SRAM array.

Peter

[ashwinkumar]

Hi Peter,

Thank you for the quick response, follow-up question on that.

Say suppose, I have single bit correctable error in RAM and it is read by processor.

The ERM interrupt gets fired (provided if enabled), our software can read the error

address register in ERM to determine the address containing the single bit error.

The question is how the software know the correct value so that it can write the value

on physical RAM ?