Cache HIT and Miss Latency

[chaitanyakumarb]

I am using MPC5777C, wanted to understand the cache HIT time and miss latency.

1) how do we compute these timings, are they standard times for all misses and hits?

2) what are the scenarios of cache flush?

are they  through

a) mtspr l1finv0 (for Data cache), mtspr l1finv1 (for instrcution cache) instruction

b) during cache replacement that is when Dirty bit is set and there is a cache miss detected or any other ways?

3) Invalidation of cache will results in cache flush also?

[davidtosenovjan]

1) If there is cache hit, there is access without wait states. If cache miss, access latency is given by access path to the target memory.

2) Both variants. Also there is instruction dcbf for that purpose.

3) No, invalidation is equal to flush only in write through mode. In the copy back mode, invalidation does not perform flush operation (i.e. does not copy line back if modified).