ADC DMA

[boxu]

I-Enviroment

MPC5746R development with S32DS and S32SDK. I want to use ADC with DMA. ADC0 Channel 0-7 and 20-25,totally 14 channels works in normal chain, software start, scan conversion mode. DMA major loop is 8, totally 14*8=112 results.

II-Problem

Channel results are not physical address consecutive,I don't know how to set DMA source address. I come up with 3 solutions:

1.SARADC0 Trigger 2 DMA channels, one transfer ADC Ch0-7 results, the other transfer Ch20-25 results. Is this method possible? But if the ADC ch is 1\2,4\5,7\8....., I need to used mutiple DMA Chs.Maybe this mehod is not good enough.

2.SARADC0 convert channle 0-25, and DMA starts after ADC normal chain. This method extends the time required for ADC and uses more ram for results buffer.

3.Enable ADC End of Chain ISR. In the ISR call back, i call SDK function for example ADC_DRV_GetConvResultsToArray, save adc results from ADC Reg to system RAM. and start DMA by software, transfer data from System RAM to finally Buffer. But this method requires CPU intervention.Is this method possible? 

III-Questions

1.Is there any other good method or anyone of the 3 above is ok?

2.What's the meaning of ADC Register: ADC_DMAE and ADC_DMAR0-2. Whether the conversion results that need to be accessed by DMA need to be set in the DMARx register. And DMA Triggerd ty ADC end of normal chain?

[PetrS]

Hi, 

I think best option is to enable DMA request for the last converted channel using ADC_DMAE, ADC_DMAR0. Within DMA you will use channel linking feature. So have 2 channels initialized, first channel, triggered by ADC DMA request, starts the second channel after finishing its major loop.
First channel will simply read ADC0 Channel 0-7 and second channels ADC0 Channel 20-25 using single major loop.

BR, Petr

[boxu]

Hello,

I have tried to use BCTU, ADC0-ADC3 triggerd by software in loop, and I can get data from BCTU ISR now. I will try to use DMA instead of BCTU ISR afterwards.

I came up with some problems about ADC3 decode channels:

1) In adc_pal of SDK, it doesn't support ADC decode channels, so I turn to use adc_sar according with bctu module;

2) In the code generated by adc_sar, exactly struct of adc_conv_config_t  in ‘ADC_SAR_DRIVER_H’, the element decodeDelay should may be 16 bits?

3)  In  the RM of Rev. 6.2 06/2017, Page 1050, ADC_DSDR Register, the DSD Tick may should be ADC_clock_frequency, not System Clock, according to my test results;

4)  I have got data from ADC0-ADC2 correcly, but the decode delay doesn't seem to work with BCTU software trigger, how should I do?(Note: Decode delay works when I test ADC modules individually.)

[boxu]

MPC5746C ADC CTU trigger external decode signal mu... - NXP Community

According to the page above, I tried to change the mode from CTU Trigger to CTU Control, and the decode delay of ADC3 works right.

[boxu]

Having trouble reading multi-channel ADC data with... - NXP Community

According to this, maybe solution1 is not working.