same issue, I have already done this dignostic step for multilink pe
Port D – Coldfire V2/V3/V4
a. BKPT (Pin-2), DSI (Pin-8), and DSCLK (Pin-4) signals are driven low.
b. RESET (Pin-7) is driven low for 20+ milliseconds and released.
c. After RESET is released and if the processor has correctly entered background mode, the PST0 (Pin-15), PST1 (Pin14), PST2 (Pin-13) and PST3 (Pin-12) lines should all be driven high by the processor.
d. Activity (changing signals) is seen on the DSI, DSO, and DSCLK signals. The activity on the DSCLK and DSI lines is
generated by the PC and the activity on the DSO line is generated by the processor.

can you give some info about how to resolve it.
Regards.