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* Owner: b21190(Vlna Peter) * Version: 1.6 * Date: Nov-11-2015 * Classification: General Business Information * Brief: Example contains startup with PLL0 200MHz as system clock * ADC self-test demonstration ******************************************************************************** * Test HW: MPC57xx * Maskset: 1N83M (cut 2.0B) * Target : internal_FLASH * Fsys: 200MHz PLL0 as system clock ******************************************************************************** Revision History: 1.0 Oct-19-2015 b21190(Vlna Peter) Initial Version 1.1 Nov-11-2015 b21190(Vlna Peter) Added PPL0 200MHz as system clock 1.2 Dec-02-2015 b21190(Vlna Peter) Added Flash controller init 1.3 Dec-02-2015 b21190(Vlna Peter) Fixed system clock init 1.4 Feb-07-2017 b21190(Vlna Peter) SWT0 and SWT1 disabled in startup 1.5 May-31-2017 b21190(Vlna Peter) Fixed comments in AC6 (CLKOUT) 1.6 Jul-10-2018 nxa13250(Vlna Peter) Added ADC self-tests *******************************************************************************/

* Detailed Description: * This example shows, how to use interrupt hardware vector mode. In the example * PIT3 and PIT2 interrupts are implemented. PIT interrupt toggle LED every second. * * * This example also shows, how to implement IVOR exceptions for core 0. * IVOR1 handler with while(1) loop is ready to use. * * * For correct HW vector mode setup, following files was added to the project: * * - exceptions.s * - handlers_vle.s * - HW_vector.c * * * Following files has been modified (all changes are marked by comment): * * - 56xx_flash.ld * - Vector.c * - MPC57xx__Interrupt_Init.c * * Following file was removed from project (files are still place in project, but * not compiled and linked) * * - intc_sw_handlers.S * - intc_SW_mode_isr_vectors_MPC5744P.c * * * * Test HW: MPC567XADAT516, MPC567XEVBFXMB * MCU: PPC5676RDMVY1 3N23A * Fsys: 180 MHz * Debugger: Lauterbach Trace32 * PeMicro USB-ML-PPCNEXUS * Target: internal_FLASH (debug mode, release mode) * EVB connection: User LED 1 connected to J241, * User LED 1 connected to J242. *

******************************************************************************** * Detailed Description: * * Application performs basic initialization, setup PLLs. * DSPI_A is configured as master using DMA to send/receive 8 words. * * Two DMA descriptors are initialized: * - TCD[32] master transmit * - TCD[33] master receive * * * EVB connection: * * Do external loopback to connect SOUT to SIN * * PM6 ... SCKA * PM7 ... SINA * PM8 ... SOUTA * PM13... PCSA0 ** * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 3N45H * Fsys: PLL1 = core_clk = 260MHz, PLL0 = 200MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * *********************************************************************************

* Owner: b21190(Vlna Peter) * Version: 1.0 * Date: May-09-2018 * Classification: General Business Information * Brief: BIST demonstration * ******************************************************************************** * Test HW: MPC57xx * Maskset: 3N23A * Target : internal_FLASH * Fsys: 200 MHz PLL with 40 MHz crystal reference * ******************************************************************************** Revision History: 1.0 Oct-22-2014 b21190(Vlna Peter) Initial Version 1.1 Mar-19-2015 b21190(Vlna Peter) Added ADC_0 driver 1.2 Mar-19-2015 b21190(Vlna Peter) Added STCU self-test for core1 *******************************************************************************/

******************************************************************************** * Detailed Description: * * Configures the MCANs to transmit and receive a CAN FD message with or without * bit rate switching for data phase. This is defined by BRS macro. * Baudrate during arbitration phase is set to 500kbps, during data phase 1Mpbs * because of PHY used on the EVB. * * In this config, MCAN_0 transmits a message. MCAN_1 receives the message. * * MCAN_0 sends message each 1sec. This interval is generated by PIT. * Single TX buffer is used to send n bytes. The message ID is changed for each * transmission. Two standard and 2 extended IDs are sent. * * MCAN_1 is configured to receive a message, ISR is used to read new message. * There are 2 standard and 2 extended ID filter tables defined. Classic filter * configuration is set, means filter ID & mask. * Messages with matched standard ID are received into RXFIFO_0, messages with matched * extended ID then stored in RXFIFO_1. * * EVB connection: * * J37 and J38 to position 2-3 to connect MCAN1 TX/RX to transceiver * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.D + MPC57xx MOTHER BOARD Rev.C * MCU: SPC5777CCMM03 3N45H * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * use USB connector (J21) on minimodule * * EVB connection: ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

******************************************************************************** * Detailed Description: * * Configure the device to wake up by STM_0 timer. * Configure the device to enter STANDBY mode from DRUN * Once the device is woken up by STM_0, the device is restared becase * we wrote address of entry point to register MC_ME.CADDR[1].R * ------------------------------------------------------------------------------ * Test HW: MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU: PPC5748GMMN6A 1N81M * Fsys: Default * Debugger: Lauterbach Trace32 * Target: internal_FLASH ********************************************************************************

******************************************************************************** * Detailed Description: * Example shows how to use original eTPU sets available over eTPU Function * Selector ( https://www.nxp.com/webapp/etpu/ ) and integrate them into * S32 Design Studio Integrated Development Platform. Example is based on * Software Development Kit (SDK) startup, in the main function adds necessary * configuration to get eTPU run. * eTPU application itself is simple PWM configured with eTPU Graphical * Configuration Tool. Target CPU is 'Generic CPU with eTPU2', eTPU clock 100MHz. * User can shows PWM waves over pins PH[10] and PH[11]. * * Tip: AN4687 may be used as reference with note the different compiler is used. * References: http://www.nxp.com/files/soft_dev_tools/doc/app_note/AN4687.pdf * https://www.nxp.com/webapp/sps/download/license.jsp?colCode=ETPUGCT * ------------------------------------------------------------------------------ * Test HW: MPC5746R-176DC Rev.A2 + MPC57xx MOTHER BOARD Rev.C * MCU: SPC5743RMLU5 QCO1640 1N83M FEAEQL * Target: Debug_FLASH * EVB connection: ETPU0_A (Port PH[10]) --> scope * ETPU1_A (Port PH[11]) --> scope * Compiler: S32DS.Power.2017.R1 * SDK release: S32_SDK_S32PA_EAR_1.8.0 * Configurator: eTPU Graphical Configuration Tool 1.4.0.4 * Debugger: Lauterbach Trace32 ******************************************************************************** Revision History: Ver Date Author Description of Changes 0.1 Apr-04-2019 David Tosenovjan Initial version *******************************************************************************/

******************************************************************************** * Detailed Description: * This example shows, how to use overlay feature - how to remap SRAM over Flash * and Flash over Flash. The remapping is visible only in mirrored flash address * space. Normal address space is not affected. To see effect of the remapping, * read the comments and watch following addresses in debugger before and after * executing Overlay() function: * * Flash over Flash test case: * 0x0104_0000 * 0x0108_0000 * 0x0904_0000 * 0x0908_0000 * * SRAM over Flash test case: * 0x4003_0000 * 0x090C_0000 * * ------------------------------------------------------------------------------ * Test HW: DEVKIT-MPC5748G * MCU: PPC5748GSMKU6 0N78S * Fsys: PLL0 160MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH (debug mode) * EVB connection: NA * ********************************************************************************

******************************************************************************** * Detailed Description: * Initializes and calibrates eQADC module and cyclically converts choosen * channel, displaying it into terminal window. * User could connect EVB pot's wiper to pin header W (see below) to see valid * conversion result. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: For ADC: J53-1 (EVB pot's wiper) --> PS0 - ANA17 * PS1 - ANA18 * PS2 - ANA19 * PS3 - ANA20 * ********************************************************************************

******************************************************************************** * Detailed Description: * * Example shows how to trigger ADC conversion on falling edge of PWM signal. * eMIOS ch1 is set to SAIC mode and a flag generated on selected edge detection * triggers BCTU channel which starts conversion of ADC1 ch9. On this channel * the board's trimmer is connected. * * EVB connection: * * J3.1 .. PA[1] - connect external PWM signal * J3.3 .. PA[2] - toggled in BCTU interrupt after ADC measurement * * ------------------------------------------------------------------------------ * Test HW: DEVKIT-MPC5748G * Maskset: 0N78S * Target : FLASH * Fsys: 160 MHz PLL * Debugger: Lauterbach * ******************************************************************************** Revision History: 1.0 Nov-5-2019 Petr Stancik Initial Version *******************************************************************************/

* Detailed Description: * This example demonstrates how to correctly execute ADC self-test for algorithm S and C. * -------------------------------------------------------------------------------------------------------------------- * Test HW: MPC57xx EVB + MPC5744P minimodule * Maskset: 1N65H * Target : internal_FLASH * Fsys: 200 MHz PLL with 40 MHz crystal reference ******************************************************************************** Revision History: 1.0 Apr-04-2016 b21190(Vlna Peter) Initial Version *******************************************************************************/