******************************************************************************** * Detailed Description: * Example demonstates Shifted PWM generating via eMIOS. * The shift is 25% duty cycle. * ------------------------------------------------------------------------------ * Test HW:  MPC5644A + XPC564A minimodule + XPC56XX mother board * Maskset:  OM14X * Target :  Internal Flash * Fsys:     16MHz IRC * * EVB settings: * PJ8 pin 0 is eMIOS CH[0] * PJ8 pin 2 is eMIOS CH[2] ******************************************************************************** Revision History: 1.0     Jun-23-2016     b21190(Vlna Peter)  Initial Version *******************************************************************************/

******************************************************************************** * Detailed Description: * This example content a basic PMPLL initialization and *  configuration of Mode Entry module and Clock Generation *  module for core1 and start of core0 and core0s from Core_Init function. * Also containts Lauterbach multicore multi-Trace32 view script for multicore * debugging puproses ******************************************************************************** * Test HW:  Test HW:  MPC57xx Motherboard + MPC5777M_512DS minimodule, MPC5777M, * Test HW:  MPC57xx * Maskset:  1N83M (cut 2.0B) * Target :  internal_FLASH * Fsys:     200MHz PLL0 as system clock ******************************************************************************** Revision History: 1.0     Jun-09-2015     b21190(Vlna Peter)  Initial Version 1.1     Sep-20-2016     b21190(Vlna Peter)  core0+core0s boot function added *******************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * start one Z7 core, interrupts initialization, ICache and DCache are disabled * on both cores because of shared memory, which must not be cached. * * There is 4K shared memory defined in the linker file. This memory is used by * both cores. Both cores access into the structure, which is placed in the shared * memory. This access is marked as a critical section. Only one core can write * to the structure at the same time. To ensure this, there are Gates, which * guarantee data coherence during the access. Only one core can be in critical * section. Second core has to wait, until first core leaves the critical section * * * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3B 0N76P * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_0 * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz *                    Z7 Core 266MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  default connection * ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows how to use eDMA for transfering 32-bit data multiple time using minor loop from internal flash to SRAM memory as well as how to configure AIPS (peripheral bridge) to grant eDMA access to peripherals. * * For closer details on how eDMA works I suggest you to check reference manual as this module is quite complex. * This example sets system clock for 200MHz running from PLL0 module. * The constant stored in internal flash is transfered via eDMA to SRAM memory. * Initialization functions are AIPS_0_Init for peripheral bridge and DMA_0_Init. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5744PE257DC minimodule, MPC5744P, * silicon mask set 0N15P * Target :  internal_FLASH* ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, setup access right for Masters and Peripherals * on AIPS_0 * * DMA transfers block of data from variable TransmitBuffer to the variable * ReceiveBuffer. Both variables are placed in SRAM. * * ICache and DCache are both disabled in startup file using CACHE_ENABLE macro. * You can change the value of the macro at the following path: * project Properties/C/C++ General/Paths and Symbols/Symbols * If you change the value to 1, ICahce and DCache will be enabled in startup. * * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3A 0N38M * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  default * ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows how to use FCCU module for fake fault injection in order to test FCCU functionality. * * For closer details on how FCCU works I suggest you to check reference manual as this module is quite complex. * This example sets system clock for 200MHz running from PLL0 module. * The FCCU_Fake_fault_inject function is setting and injecting FCCU fault NCF[7] - STCU2 fault condition. * Short reset is triggered as soon as FCCU registers injected fault. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5744PE257DC minimodule, MPC5744P, * silicon mask set 1N65H * Target :  internal_FLASH* ********************************************************************************

******************************************************************************** * Detailed Description: * * eQADC mode: Continuous scan with external trigger. * Periodic trigger from eMIOS_0 ch16. * ANA ch5 is converted and result is sent to RFIFO0. * * eMIOS ch0 duty cycle is modified based on result data, so LED is dimming * if connected to eMIOS ch0 output. * * ADC result is also displayed on terminal each second. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *           use USB connector (J21) on minimodule * * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * *           eMIOS ch0 (PortG P14-16)--> USER_LED_4 (P7-4) *                  ANA0       (PortQ P24-5) --> RV1 (J53.1) * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, * initializes and display notice via UART terminal and then terminal ECHO. * * * ------------------------------------------------------------------------------ * Test HW:         MPC5604EEVB64 * MCU:             PPC5604EEMLH 0N10D * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFLEX_0 * Fsys:            40 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  JP17 connected to J38.7 (ADC CONN), jumpers J7,J8 position *                  2-3 fit SCI tx and rx connected * ********************************************************************************

# README This is a mcan sdk demo on MPC5777C. Transmit data in turn and received data. CANFD is not used and extended id is used. Both Tx and Rx use interrupt. All documents are in [mpc5777c_test_mcan/mpc5777c_test_mcan_Z7_0/Documentation] folder. ## Board MPC5777C-416DS + MPC57xx MOTHERBOARD (SCH-27237 REV C) ## CAN PC Client PCAN-View ## Compiler powerpc-eabivle-gcc with S32 Design Studio for Power Architecture IDE ## MCAN MCAN0 ## Pin PC[19] - MCAN0 Tx PC[20] - MCAN0 Rx ## SDK S32_SDK_S32PA_EAR_1.8.0 ## Caution 1. Error to send data bytes which are not multiple times of 4 with MCAN_StartSendData() in mcan_driver.c. So MCAN_StartSendData() must be modified. Modified position is 606 to 607 lines in mcan_driver.c. 2. MCAN_DRV_InstallEventCallback() hasn't been implemented yet, must be added. ## Revision History Release 1.0.0 - 2018/12/19 - Jacob Peng - jacob.peng@nxp.com * Mod: MCAN_StartSendData() in mcan_driver.c * Add: MCAN_DRV_InstallEventCallback() in mcan_driver.c * Add: Demo application

This example performs LED toggling using hardware vector mode.   *UPDATE* - Internal RAM function was added, fixed exceptions, * * Detailed Description: * - 1 second LED1 toggle using emios interrupt * - LED2 toggle using irq 0 interrupt via sw_button1 * - 1 second LED3 toggle using Decrementer via IVOR10 * - hardware vector mode configuration for interrupts * * ------------------------------------------------------------------------------ * Test HW:  MPC5566 EVB MOTHERBOARD, PPC5566 MVR132 * Target :  Internal Flash, Internal RAM * Fsys:     80 MHz PLL with 8 MHz crystal reference * * ------------------------------------------------------------------------------ * EVB connections and jumper configuration * * MPC5566 EVB MOTHERBOARD * * LED1 D17 * LED2 A17 * LED3 C16 * For SW1 is used pin 2 and it is connected to AF19 * *********************************************************************************

******************************************************************************** * Version:          1.0 * Date:             Oct-22-2014 * Classification:   General Business Information * Brief:         This example demonstrate SWT functionality *                   On SWT timeout it sent signal to FCCU where is short *                   functional reset reaction on SWT timeout configured *                   FCCU then sent signal to RGM module which triggers short *                   functional reset. ******************************************************************************** * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference ******************************************************************************** Revision History: 1.0     Oct-22-2014     b21190(Vlna Peter)  Initial Version 1.1        Mar-24-2015       b21190(Vlna Peter)  Added SWT short reset *******************************************************************************/

External Bus Interface FAQs related to MPC55xx and MPC56xx MCUs Preliminary version

WARNING 1: Use censorship feature very carefully, because an inappropriate usage can lead in making the device useless!!! Thoroughly read all instructions before use!!!   WARNING 2: Version of ICDPPCNEXUS debugger that is included with CodeWarrior 2.10 is not capable to enable debug on certain devices including MPC5604B. Workaround is either using of Codewarrior 10.6 or using of PKGPPCNEXUS debugger - can be downloaded from P&E Microcomputer Systems   WARNING 3: In case TRACE32 debugger is being used (Lauterbach), it is needed to have updated TRACE32 software. TRACE32 releases 02/2015 and 09/2016..02/2018 may not be able to access to censored device. LAUTERBACH DEVELOPMENT TOOLS   The example consists of 2 parts and document describing how to access censored device via JTAG with using of PeMicro or Lauterbach debugger:   1) MPC5604B-Censor_device-CW210: ******************************************************************************** * Detailed Description: * The example code reprogram content of shadow flash to enable censorship. * After succesful operation LED1 is lighting. After power-on-reset the device * is censored with private 0xFEED_FACE_CAFE_BEEF. Subsequently the access can be * allowed by enabling debug of censored device as decipted in attached pdf * document. On this device password must be entered in reverse order i.e. * 0xCAFE_BEEF_FEED_FACE. Shadow flash re-programming code must be executed from * internal RAM. * ------------------------------------------------------------------------------   2) MPC5604B-Uncensor_device-CW210: ******************************************************************************** * Detailed Description: * Supposing the device is censored by example MPC5604B-Censor_device-CW210 * Firstly it is needed to enabled debug of censored device as decipted in * attached pdf document. On this device password must be entered in reverse * order i.e.0xCAFE_BEEF_FEED_FACE. MPC5604B_run_from_ram.cmm script does it by * command SYStem.option.keycode 0xCAFEBEEFFEEDFACE. * Then run this code to uncensor the device. After succesful operation LED1 is * lighting. After power-on-reset the device is uncensored and subsequent access * will be without password. Shadow flash re-programming code must be executed * from internal RAM. * ------------------------------------------------------------------------------

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, Setup access right for Masters and Peripherals * on AIPS_0 * * LINFlex UART mode with FIFO transmit using DMA * LINFlex UART mode with FIFO receive using DMA * * ICache and DCache are both disabled in startup file using CACHE_ENABLE macro. * You can change the value of the macro at the following path: * project Properties/C/C++ General/Paths and Symbols/Symbols * If you change the value to 1, ICahce and DCache will be enabled in startup. * * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3A 0N38M * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_0 * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  J14.2 to P12.6 Connect LINFlexD_0 RXD to main RS232 *                  J13.2 to P12.7 Connect LINFlexD_0 TXD to main RS232 * ********************************************************************************

******************************************************************************** * Detailed Description: * This example content a driver for ADC module. * Basic ADC functionality is demonstrated via ADC_0 normal conversion for ADC_0 AN0 channel. * * For closer details on how ADC works I suggest you to check reference manual. * This example sets system clock for 200MHz running from PLL0 module. * Example contains basic ADC functionality demonstration. Software is starting normal ADC conversion * on ADC_0 channel AN0. * To demonstrate the measurement functionality on Freescale MPC57xx motherboard connect jumper to J53. * By doing this the potentiometer is connected to AN0 ADC input. For further details see MPC57xx EVB schematics. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5744PE257DC minimodule, MPC5744P, * silicon mask set 1N65H * Target :  internal_FLASH* ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, second LED by software * loop, third LED by second core, initializes and display notice via UART * terminal and then terminal ECHO. * * ------------------------------------------------------------------------------ * Test HW:  XPC56xxMB2 + XPC564xB/C, PPC5646C 0M87Y silicon * Target :  internal_FLASH, RAM * Fsys:     120 MHz PLL0 * Debugger: Lauterbach Trace32. script for internal_FALSH run_from_flash.cmm *                               script for RAM: run_from_ram_vle.cmm * ********************************************************************************

******************************************************************************** * Detailed Description: * Initializes eQADC module, converts specified command queue and displays * results into terminal window when EOQ is reached. Used analog inputs ANA_0 and * ANA_1 requires external connection to converted voltage (potentiometer) to * see some valid numbers. For simplicity, ADC module is not calibrated. * ------------------------------------------------------------------------------ * Test HW:         XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU:             PPC5674FMVYA264 * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys:            264/200/150/60 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  Potentiometers     --> ADC inputs *                  USER_DEV_RV2(J4-7) --> ANA_0 (J18-3) *                  USER_DEV_RV3(J4-8) --> ANA_1 (J18-4)                * ********************************************************************************

******************************************************************************** * Detailed Description: * * Unlock, erase and program of flash mid block 0x00FB_8000 - 0x00FB_FFFF. * ------------------------------------------------------------------------------ * Test HW:        X - PC5748G - MB (rev C) * MCU:             PPC5748GMMN6A * Maskset:       1N81M * Fsys:             160 MHz * Debugger:     Lauterbach Trace32 *             * Target:     Internal_FLASH * ********************************************************************************

******************************************************************************** * Detailed Description: * * Example shows MCU's temperature measurement with the help of TSENS. * Calibartion constants for TSENS0 and TSENS1 are read from Test Flash and * ADC0/ADC1 is set to measure Vbg and TSENS outputs. * Calculated internal temperature can be desplayed on the Terminal. * * EVB connection: * *   Route LINFlexD_0 TXD/RXD (PB2/PB3) signals to the main board RS-232 transceiver *   Daughtercard: *   J17.11–12 ON  .. Connect LINFlexD_0 TXD (PB2) to main board. *   J17.8–9 ON .. Connect LINFlexD_0 RXD (PB3) to main board. * *   Motherboard *   J14 - SCI_RX ON *   J13 - SCI_TX ON *   J25 - SCI_PWR ON * * See results on PC terminal (19200, 8N1, None). You should get following text * (with different values for sure) * * TSENS0/TSENS1 temperature measurement * press any key to continue... * * Calibration constants read from Test Flash * * TSENS0                           TSENS1 * * K1 = 429                         K1 = -220 * K2 = -5785                       K2 = -5767 * K3 = -12800                      K3 = -12736 * K4 = 45                          K4 = 45 * *      K1 * Vbg_code * 2^-1 + K2 * TSENS_code * 2^3 * T = ------------------------------------------------------------------------- / 4 - 273.15 [degC] *     [K3 * Vbg_code * 2^2 + K4 * TSENS_code] * 2^-10 * * Vbg0_code      = 1502               Vbg1_code      = 1502 * TSENS0_code = 2002               TSENS1_code = 1988 * * TSENS0 temp = 34.57 degC         TSENS1 temp = 36.78 degC * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N65H * Target :  RAM, internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference * Terminal: 19200, 8N1, None ********************************************************************************

******************************************************************************** * Detailed Description: * Inject and handles HVD and LVD faults. Application also configures FCCU_F pins * to see possible faults externally - normally these two pins toggles antiphase, * in case error these pins toggles inphase. If you step the code not allowing * alarm interrupt to be handled on time, device goes to safe mode and FCCU_F * pins toggles in phase. * ------------------------------------------------------------------------------ * Test HW:         xPC564xLKIT, PPC5643L Cut3 silicon * Target :         internal_FLASH, RAM * Fsys:            120 MHz PLL0 * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Terminal:        19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection:  FCCU_F0 and FCCU_F1 connected to the scope - pay attention to *                  J16 and J18 jumpers on mini-module (FCCU_F0 and FCCU_F1). * ********************************************************************************