Example MPC5777C-1b+2b_FLASH_ECC_error_injection GHS614

[#1]

********************************************************************************
* Detailed Description:
* Purpose of the example is to show how to generate Multi-bit or Single-bit
* ECC error in internal FLASH (user must choose it in the option at the end of
* main function).
* Flash over-programming is used to generate a non-correctable (or single-bit)
* ECC error in FLASH. The bad data is accessed then, so the IVOR1 exception (or
* ERM combined interrupt service routine) is generated and handled.
* Example also offers useful macros for EIM and ERM modules.
* The example displays notices in the terminal window (USBtoUART bridge J21)
* (19200-8-no parity-1 stop bit-no flow control on eSCI_A).
* No other external connection is required.
*
* ------------------------------------------------------------------------------
* Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C
* MCU:             PPC5777CMM03 2N45H CTZZS1521A
* Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz
* Debugger:        Lauterbach Trace32
* Target:          internal_FLASH
* Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A
* EVB connection:  eSCI_A is USBtoUART bridge (connector J21)
*
********************************************************************************

[yvesbriant]

Hello David,

I wonder why you chose to generate Flash ECC errors by a double-program operation in flash. MPC5777C (and others MPC57xx devices) do have some area in flash which are programmed to contain a single or double ECC error. You only need to read these locations to have a single/double ECC error be generated.

Thanks