Voltage detect interrupts on FDRM-MCXN947

[robert_hines]

I'm trying and failing to throw LVD/HVD interrupts.  I'm using the USB for part of the power and for programming/UART over the on board MCU-link.  I'm separately powering P3V3_MCU at jumper J24.  I've set the appropriate SPC registers, disabling reset and enabling interrupt (LVDIE=HVDIE=1, LVDRE=HVDRE=0 in the VD_xxx_CFG registers).  I've written something for SPC_IRQHandler and have enabled the SPC interrupt (EnableIRQ(SPC_IRQn)).

When I crank down the voltage on P3V3_MCU, reset triggers around 2.63V but the interrupt doesn't trigger.  It also looks like there are multiple drivers on the RESET_b line; the MCX_RST goes from bright to dim when I increase the voltage, and I have to power cycle to clear the reset.

Is the MCU-link interfering somehow?  Why do I get reset and not the interrupt?  What is pulling down the reset line?

Any ideas?  Or better ways to test the LVD/HVD?

[robert_hines]

The reset behavior of the ITRC registers is not as described in the security reference manual.  In particular

ITRC OUT4 (16-31): aaaaaaa5

which says that low-voltage detect on VDD_IO should reset the chip.  Changing this allows the VDD_IO LVD to trigger the SPC interrupt as desired.  Similarly for the HVD.

[Alice_Yang]

Hello @robert_hines 

Thanks for your reply.

" Changing this allows the VDD_IO LVD to trigger the SPC interrupt as desired.  Similarly for the HVD."

->> It seems that you have resolved your issue. Could you please share which part you changed? Thank you in advance!

BR

Alice

[robert_hines · Accepted solution]

The ITRC was resetting the chip (OUT4) on VDD_IO_LVD (IN17) and this apparently has higher priority than the SPC interrupt.

The reset values of the ITRC registers don't seem to match those listed in the security reference manual, so they had to be changed to disable OUT4 on IN17 in order to prevent reset and hand the SPC interrupt.

Basically, every possible reset source triggered by LVD needs to be disabled before the SPC interrupt is useful, and the ITRC was an "unexpected" source of such a reset.  In other words, disabling reset and enabling interrupt in VD_IO_CFG is not enough to ensure that other reset sources triggered by LVD are disabled.

[robert_hines]

Doesn't seem to be a way to edit my question.  Here are a few other things I've tried:

In VD_IO_CFG, the LVSEL bit seems to work (changing it changes when the reset occurs), but the LVDIE/LVDRE bits aren't affecting behavior.

Disabling voltage detect in ACTIVE_CFG (e.g. 0x0010---- instead of 0x3F10----) works as expected, disabling the reset.

Forcing the SPC interrupt with NVIC_SetPendingIRQ(SPC_IRQn) works as expected.

I've also tried disconnecting the USB and powering P3V3 directly, with the same results.

[Alice_Yang]

Hello @robert_hines 

Thanks for contacting us.

Please confirm that the LVD/HVD modules are not configured as reset sources. For details, please refer to the MCXN947 Reference Manual.

Thank you.

BR

Alice

[robert_hines]

I have the VD_xxx_CFG SPC registers set to 0x0000000A, i.e. HVDIE=LVDIE=1, HVDRE=LVDRE=0.  I also have ACTIVE_CFG configured appropriately.

One of the problems (the strobing reset line) is on NXPs end (https://www.nxp.com/docs/en/errata/MCXN_1P02G.pdf  "ERR052476: ROM: Infinite reset loop entered when LVD event occurs"

Updating the boot ROM did fix the reset strobing, but I still can't get interrupts, only resets.