UART overrun error occurs when set rx fifo watermark

[wasdqwerfzxcv]

Good morning,

I am developing a project based on MCXA132VFT. I am facing issue that with the configuration below UART overrun error occurs when receiving UART data 

However, the UART overrun error didnt occurs if I set the RX FIFO watermark to 0. (Even the RX FIFO watermark is just 1 instead of 3 UART overrun error still happens) 

Besides, from the reference manual seems like overrun flag is set to 1 when receiving data while RDRF flag is 1.  Since RDRF flag is set to 1 when the number of data in the RX FIFO is greater than the watermark so is this means overrun flag will be triggered even though RX FIFO is not full? 

Thank you very much for your time and help.

Best regards

[Harry_Zhang · Accepted solution]

Hi @wasdqwerfzxcv 

When the RX FIFO watermark (RXWATER) is set higher than 0, the RDRF flag becomes 1 before the FIFO is actually full. If the software does not read out the FIFO fast enough after RDRF=1, new incoming bytes can fill the FIFO completely, and once it’s full, the next received character causes the overrun error.

When you set RXWATER=0, the interrupt triggers earlier—after just one received byte—so your software has more time to read data, preventing FIFO full conditions and avoiding overrun.

Therefore, the overrun flag is not triggered just because RDRF=1, but only when the FIFO is full and another new character arrives. However, setting the watermark too high increases the risk that the FIFO becomes full before your software empties it.

So i think you can Keep RXWATER = 0 if you want earliest interrupt and minimal risk of overrun.

Or, if using RXWATER > 0, ensure:

UART RX interrupt has high priority.

BR

Harry