MX6SLL DDR3 signal length

[vlintilhac]

Hi,

In the Hardware Development Guide for i.MX 6SoloLite Applications Processors (IMX6SLHDG), pages 39-40, the Table 2-5. Total signal etch (DDR3) shows a clock signals almost double the length of other DRAM signals.

Is there an explanation to the extra length of the SDCLK signals?

Do you have any info on the internal pin delay that could explain this design choice?

Vincent

[JorgeCas]

Hello,

This length values are defined by the DDR controller and pin delays.

The package delay information is explicitly provided only for the DDR signals in the HDG document. However, the package delays of the other pins can be quite precisely estimated by taking the IBIS model and calculating the delay from the L_pin and C_pin values assigned for each pin by using the following formula:

delay = sqrt(L_pin*C_pin)

Best regards.