MCXN947 GPIO5 clock

[chrisgulick]

Which clock is used for GPIO5. I see gpio0-4 but 5 is missing.
Which kCLOCK is used for GPIO5/PORT5. Thank you.

excerpt from fsl_clock.h

kCLOCK_Port0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /*!< Clock gate name: Port0. */

kCLOCK_Port1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /*!< Clock gate name: Port1. */

kCLOCK_Port2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /*!< Clock gate name: Port2. */

kCLOCK_Port3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), /*!< Clock gate name: Port3. */

kCLOCK_Port4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), /*!< Clock gate name: Port4. */

kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /*!< Clock gate name: Gpio0. */

kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), /*!< Clock gate name: Gpio1. */

kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), /*!< Clock gate name: Gpio2. */

kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), /*!< Clock gate name: Gpio3. */

kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), /*!< Clock gate name: Gpio4. */

[Harry_Zhang]

Hi @chrisgulick 

According to MCXN947 Reference Manual.

slow_clk provides the bus clock for gpio5.

Its status is enabled by default.

Hope this will help you.

BR

Hang

[chrisgulick]

Thank you. I did notice the slow clock for gpio5 but did not know it was on by default. Good to know I will give it a try and toggle my gpio based on port5.

[chrisgulick]

I also discovered port 5.2 defaults to ALT1. It needs to be set to ALT0 for gpio use. But it is working now as gpio for me. The fun begins.