Hello,
I'm using the MCXN947 via FlexSPI with an OctalRAM (IS66WVO32M8DALL-200BLI).
The FlexSPI root clock is supplied at 150 MHz via PLL1, and since the RAM operates in DDR mode, I have an output clock rate of 75 MHz.
The `flexspi_device_config_t` has the following parameters:
flexspi_device_config_t psram_config =
{
.flexspiRootClk = 150000000U,
.isSck2Enabled = false,
.flashSize = OCTALRAM_ISSI_SIZE,
.CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
.CSInterval = 2,
.CSHoldTime = 2,
.CSSetupTime = 2,
.dataValidTime = 2,
.columnspace = 4,
.enableWordAddress = false,
.AWRSeqIndex = HYPERRAM_CMD_LUT_SEQ_IDX_WRITEDATA,
.AWRSeqNumber = 1,
.ARDSeqIndex = HYPERRAM_CMD_LUT_SEQ_IDX_READDATA,
.ARDSeqNumber = 1,
.AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
.AHBWriteWaitInterval = 0,
.enableWriteMask = true,
};
To initialize FlexSpi, I use the SDK FLEXSPI_DRIVER, version 2.6.0.
When I configure the delay cells using the auto-adjusted function (as described in the manual under section 10.3.15.6, “DLL configuration for sampling”) with the following values:
• SLVDLYTARGET=0x0F (divider 16/32 * root_clock = 3.33 ns)
• REFPHASEGAP=0x02
• DLLEN=0x01
• OVRDEN=0x01
After waiting for the ASLVLOCK and AREFLOCK lock bits, I get 0x01 for ASLVSEL and 0x00 for AREFSEL. Consequently, the RAM's read and write functions do not work, since the set delay time is approximately 120 ps!
/* Configure DLL. */
configValue = FLEXSPI_CalculateDll(base, config);
base->DLLCR[index] = configValue;
/* DLL neu kalibrieren */
base->DLLCR[0] |= FLEXSPI_DLLCR_DLLRESET_MASK;
base->DLLCR[0] &= ~FLEXSPI_DLLCR_DLLRESET_MASK;
/* Exit stop mode. */
base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
/* Lock abwarten */
while ((base->STS2 &
(FLEXSPI_STS2_AREFLOCK_MASK |
FLEXSPI_STS2_ASLVLOCK_MASK)) !=
(FLEXSPI_STS2_AREFLOCK_MASK |
FLEXSPI_STS2_ASLVLOCK_MASK))
{
}
SDK_DelayAtLeastUs(10U, CLOCK_GetCoreSysClkFreq());
Even if I use different values for SLVDLYTARGET, the output of ASLVLOCK and AREFLOCK does not change.
However, if I set the delay time to a fixed value using the registers OVRDEN=0x01 and OVRDVAL=0x1b (corresponding to a delay time of approximately 3.36 ns), reading from and writing to RAM works without any problems.
However, since the root clock is greater than 100 MHz, NXP recommends using the DLL's auto-adjustment feature.
Unfortunately, it doesn't seem to be able to determine the correct delay time!
Hi @IbhDaniel
Thank you for the post!
The MCXNx4 Reference Manual indicates that the serial root clock is the FlexSPI core clock (see Table 79. Clock Usage). In your case, this clock is configured to 150 MHz.
I also see that you have implemented the DLL sampling configuration, and the auto-calibration path appears to be the correct approach. The settings SLVDLYTARGET = 0x0F and DLLEN = 0x01 were configured correctly. The only issue identified was OVRDEN = 0x01 instead of 0x00, which disables the auto-calibration output path and causes ASLVSEL = 0x01 and AREFSEL = 0x00 regardless of the SLVDLYTARGET value.
I would just like to confirm that the above analysis applies to your implementation. Could you please verify that: MCR0[RXCLKSRC] = 3h (Flash-memory-provided read strobe and input from DQS pad) is being used in your configuration?
