@qwerty1123
ECC can be enabled and errors can be detected by the DDRC hardware, but you should not expect an existing Linux EDAC driver for i.MX 8QXP sideband ECC unless you have a BSP/private patch outside the retrieved sources. A board-specific driver would need to map the DDRC ECC registers from AN13566, handle ECC_CORRECT_INT / ECC_NCORRECT_INT , read ECCSTAT / ECCERRCNT , clear through ECCCTL , and optionally register with the Linux EDAC framework.
The app note describes correctable, uncorrectable, and AP error interrupt enables and status handling through DDRC registers. So, you most probably have to write a custom driver for it.