Hi,
I'm testing the inference time and performance of TFLite AI Models on the NXP FRDM-MCXN947 MCUs. While I'm getting good performance using the NPU, I'm getting comparably slow inference times when not using it. I have been able to reduce inference time for other MCUs by enabling the Data Cache. I would like to know how to enable D-Cache on the NXP MCUs. Any other performance boost strategies are also welcome.
Interesting! Have you experimented with compiler optimization flags? Often, bumping up optimization (e.g., -O3) can significantly speed up code when the NPU isn't active. Also, regarding D-Cache, check the SDK documentation for CACHE_Enable or similar functions, specifically for the MCXN947. Remember optimizing often comes down to a balancing act like in Slope Game, optimizing code versus hardware limitations for top performance. Good luck!
It's great to see you exploring TFLite AI Models on the NXP FRDM-MCXN947! Enabling D-Cache can indeed enhance performance significantly. You might also look into optimizing your model size or quantizing your models for better efficiency. Speaking of performance, have you tried integrating it with gaming applications like the Snow Rider 3D game? It could be a fun way to test the capabilities of your setup!
Hi Harry,
Could CACHE64 be data cache and LPCAC be Instruction cache?
Hi Harry,
I was going through the reference manual and SDK drivers as you mentioned:
I noticed theres is
* fsl_cach_lpcac.h which contains L1CACHE_EnableCodeCache()
and
* fsl_cache.h which contains CACHE64_EnableCache(CACHE64_CTRL_Type *base)
Could CACHE64 be data cache and LPCAC be Instruction cache?
The CACHE64 module is used to cache FlexSPI accesses.
Based on your need, you just need to enable lpcache.
BR
Harry
You can refer to the Chapter 5 in MCX Nx4x Reference Manual.
Regarding cache related APIs.
You can refer to the fsl_cache_lpcac.h in MCXN947 SDK.
BR
Harry