32-Bit Parallel Receive on Rising Edge Pin (FRDM-MCXN947)

[Flexin_On_The_IO]

I am currently trying to configure a 32-bit parallel Shifter to receive data from an external device with one of the pins (FLEX_D4/DATA_VALID) being used as a signal to Shift in the data. 

The progress I have made has allowed me to read in the 32-bit data when DATA_VALID has triggered and move the data into an eDMA Ping-Pong buffer. I am currently testing through Printf statements of reading the buffer data to a console and if the Shifter has any errors (usually indicating Overrun according to the datasheet) they will print to the console as well. 

I believe my main issue is with the TimerConfig as it is triggering the Shifter to read too many times on one rising edge of DATA_VALID but I have not found a configuration that allows me to read only once while actually moving the correct data. 

Console Output: 

Reading Buffer A: 0x3fffefff
Shifter Error Code: 0x8
Shifter Status: 0x0
SHIFTSDEN: 0x8
DMA CSR: 0x0
DMA Error: 0x0
TCD BITER: 0x2 CSR: 0x12
CH_MUX: 0x40

Reading Buffer B: 0x3fffefff
Shifter Error Code: 0x8
Shifter Status: 0x0
SHIFTSDEN: 0x8
DMA CSR: 0x0
DMA Error: 0x0
TCD BITER: 0x2 CSR: 0x12

My FLEX_IO setup is attached. Thank you.

[Flexin_On_The_IO]

Update: I was able to deduce that "kFLEXIO_TimerDisableOnTriggerFallingEdge" was keeping my CPU in the callback.

I believe I want to disable after a Timer Compare but with this option SHIFTBUF only reports a value of 0x0 but with no SHIFTERR flag. 

[carlos_o]

Hi  @Flexin_On_The_IO 

Thank you for your post!

Could you please share the current behavior you see in your register? 

Which test data are you trying to receive and what you currently get? 

Could you please share which MCXN are you using? 

Is it a custom board? if not, please specify the board you are using

[Flexin_On_The_IO]

Hi @carlos_o thank you for the reply!

I was able to get the Timer reading on DATA_VALID edge like I wanted but did not update the thread. My current code is attached.

The problem I am facing now is getting the FlexIO to keep up with other devices. In my current setup I am basically sampling DATA_VALID and at higher speeds, the Shifter can get Overrun. My thinking is that my design requires a shared clock between the MCX & host device that would be sending the 32-bit data. I can use a pin within the 32-bit data bus to be this signal so I do not need to breakup the FlexIO pins. Any input on this idea would be welcome!

To answer your previous questions:

1. The registers are populating as intended at lower speeds. On every DATA_VALID falling edge, the SHIFTBUF stores data from the 32 Pins and the EDMA transfers to my Ping-Pong buffer via a Scatter-Gather method.

2. I am simulating input through an Analog Discovery 2, since that only has 16 data pins I am just writing the upper values of the 32-bits, simulating a clock on the DATA_VALID pin, and tying the unused pins down. Test data is matching correctly at low speeds.

3. I am using the FRDM-MCXN947

[carlos_o]

Hi @Flexin_On_The_IO 

Apologize the late reply, 

Could you please specify the speeds you are trying to achieve? 

You could review AN14284: Timing Parameter Tuning for FlexIO Emulated Interface, this app note could have some helpful information to your goal.

[Flexin_On_The_IO]

Hello again, @carlos_o 

The bare minimum speed I am trying to reach is 18.5MHz. I can confirm the Shifter does keep up at around 6.25MHz but I was having issues at higher speeds due to my hardware limitations :P. 

Below is my Analog Discovery 2 waveform where I am just providing the MCLK signal, a binary counter for the data (12-bit only due to low pin count on AD2), and manually controlling the DATA_VALID signal. 

Flexin_On_The_IO_0-1783689475176.png

When I get to higher frequencies (20 MHz) I realize the AD2 cannot actually provide a decent square wave and may be causing my FRDM to trigger undesired Shifts due bad signal integrity. 

Flexin_On_The_IO_1-1783690391552.png

I was looking at the file you sent me and I think it may be a solution to an issue I want to take care of. If DATA_VALID rises/falls at the same time as MCLK I believe it misses the a Shift of data since the clock was not able to fully decrement.

My main question is do the Shifters usually require a delayed clock/Timer in order to complete their full shift cycle even after the Trigger from the other device has gone low? My current setup requires the DATA_VALID to remain high between MCLK edges to not miss the data.