The MCX  N series are MCUs with an integrated flash memory like many traditional MCU series. Having an embedded flash memory is particularly useful, as facilitates board design, development, simplifies BOM, software development.  However, the size of the embedded flash might not meet applications required memory footprint. Some customers simply need more flash memory. For example, Graphical applications require store large image buffers in a non-volatile memory. Data logger devices that need to store large amounts of data. Or heavy inference models for object recognition.  Applications that need to store backup versions of their firmware or are way too complex and big. To solve this requirement the MCX N94x provides the capability to interface a great variety of wider and external memories. There are several traditional options to expand flash storage, but the one we are addressing is the use of external NOR  flash memories. To access an external memory the MCX N94x integrates modules that support external memory interfacing, those are  FlexIO and the FlexSPI. The FlexSPI module is capable of communicating with several kinds of memories. One of them is the Serial NOR flash which can be used as booting device. The goal of this article is to present the solution of a customer case scenario: How to run code from an external flash memory. Demonstrating the flexibility of the MCX N94x platform as well as introducing several tools, peripherals, and concepts that a developer will need to be familiar with while developing an application that runs from an external flash memory. The below figure illustrates the goal of this article, Run code from an external flash memory. The same hello world application can be run from the internal and external memory, for example, a NOR serial QuadSPI memory, without any functionality changes. The core simply will fetch and execute the instructions, using dedicated peripherals like FlexSPI.   Figure 1 Executing same code from internal memory vs external memory. The MCX N94x series integrates a FlexSPI module, which enables running code from an external NOR flash memory.   Figure 2 MCX N94x block diagram To follow this article, you will need the  FRDM-MCXN947 Development board. Which is the evaluation board for the MCX N94x and N54x MCUs. The FRDM-MCXN947 integrates a W25Q64JVSSIQ QuadSPI flash memory. Therefore, this platform is perfect for creating an application that runs from an external flash memory. Figure 3 External NOR flash memory on FRDM-MCXN947   Boot, PFR, and SPSDK   With the boot ROM  that the MCX  N integrates you can erase, program, and read the on-chip or external flash memory, which means you can use the boot ROM to download a boot image into the on-chip or external flash memory via the ISP interfaces. This article shows how to load a customized led_blinky demo, from the SDK  to the external flash memory using the boot ROM. However, other application projects may be used as well. Also, the boot ROM takes responsibility for the boot flow. It selects whether to boot from on-chip flash memory, external flash memory, or ISP mode.  The figure below shows an extremely simplified boot flow, which gives an overall understanding of the chip boot flow.  For more details on the boot flow mechanism refer to the section Top-level boot flow of the MCX Nx4x Reference manual.   Figure 4 Simplified boot Flow After the reset handling routine, the boot ROM will take control of the chip’s boot flow. It will begin with pertinent chip’s initialization. Then will check the status of the ISP pin. If the ISP pin is currently asserted, the ISP boot handling routine will be executed. ISP or  In-system programming is an execution mode where the boot ROM will wait for commands from an external host, over protocols like UART or USB, to do actions like read and write the chip memory, burn fuses, and many more. If the ISP pin is not asserted, the boot ROM will continue to determine the boot mode. Boot mode can be controlled with the CMPA[BOOT_SOURCE] bit of the CMPA of the PFR or eFUSES. If  CMPA[BOOT_SOURCE]= 01b the boot ROM will run FlexSPI NOR boot handling routine. If CMPA[BOOT_SOURCE] is 00b or 11b internal flash memory handling routine is executed. After the boot mode selection, the image will be validated. If it is not valid, for example, is not present in memory, is corrupted, or does not have proper format,  the ISP boot handling routine is executed. If the image is valid, finally the boot ROM will perform the jump to the user´s application. The default boot flow is by internal flash, most of the SDK examples will be configured to boot from internal flash, as CMPA[BOOT_SOURCE] equals zero by default, or when CMPA area is erased. According to the Simplified bot Flow diagram, we need to make boot ROM go to FlexSPI NOR boot handling routine, to boot from the external flash. Therefore, we need to make   CMPA[BOOT_SOURCE] = 01b. The PFR holds critical boot and security settings that are monitored by the boot ROM after every reset. As just described earlier, the CMPA area can be used to control boot mode. Therefore, PFR areas need to be carefully configured, as they control boot flow and also security features of the chip. The below figure shows a very minimalistic representation of the PFR containing the CMPA, next to the internal flash.   Figure 5 PFR's CMPA area   For specific details of the PFR  please refer to the MCXNx4x_IFR.xlsx, attached to the MCX Nx4x Reference Manual. To facilitate writing into the CMPA and other areas of the  PFR, signing applications, burning fuses.  programming applications, NXP already developed several host command tools, APIs, and applications and integrated into a python tool called SPSDK. The below figure shows all the tools contained by the SPSDK. To get  details on the SPSDK and description of APIs, Applications, and tools  refer to SPSDK documentation at  https://spsdk.readthedocs.io/en/latest/spsdk.html#   Figure 6 SPSDK API modules, applications, and tools The above figure highlights 3 applications, provided by the SPSDK,  that is going to be used to configure the chip to boot from the external flash memory those are: nxpdebugmbox, PRF, and BLHOST. Detailed step-by-step usage of these applications will be described later on.  The nxpdebugmbox application sends interfaces with the chip’s debug mailbox over SWD. The purpose of this tool is set MCU into ISP mode, without having to set low ISP pin,  also to make a mass erase to the chip's memory and PFR. Once the MCU enters ISP mode the host PC will be able to communicate with the boot ROM over UART or USB protocols. This enables the use of PFR and BLHOST applications. The PFR application will be used to write the CMPA[BOOT_SOURCE] = 01b and enable FlexSPI, port to probe and let the chip communicate with the external flash, in the CMPA area of the PFR. The BLHOST application will be used to erase the chip and program application image, in this particular case,  a led_blinky demo.    External Serial NOR flash interfacing   The following terms are critical to understand how we can execute code in an external NOR flash memory with the MCX N94x. First of all, Execute-in-Place refers to the capability that the MCU core has to fetch and execute instructions directly from the external memory. It refers to the capability that an MCU has to execute code from the flash memory instead of an internal and traditional flash. To do XIP the MCX  N94x requires a capable peripheral with the ability to fetch instructions from the external memory. The FlexSPI module is capable of doing this. The FlexSPI does support several types of external memories. One of them is Serial NOR Flash. To interface the external memory with the FlexSPI supports SPI. SPI is an excellent serial protocol for short-distance and high-speed communications. The term QuadSPI could be simply understood as an implementation of the SPI protocol, where instead of having a single Data line, there are 4 data lines. SPI also supports two, and eight data lines. Flexible Serial Peripheral Interface (FlexSPI) memory controller supports connection to external serial NOR, NAND, and RAMs. It supports two SPI channels and up to four external devices. Each channel supports Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional data lines). Flexible sequence engine (LUT table) to support various vendor devices (serial NOR, serial NAND, HyperBus, FPGA, etc). Memory-mapped read/write access by AHB Bus AHB RX Buffer implemented to reduce read latency. Total AHB RX Buffer size: 1024 Kbytes 8 flexible and configurable buffers in AHB RX Buffer Software triggered Flash read/write access by IP Bus IP RX FIFO implemented to buffer all read data from External device. FIFO size: 1024 Bytes IP TX FIFO implemented to buffer all Write data to External device. FIFO size: 1024 Bytes DMA support to fill IP TX FIFO DMA support to read IP RX FIFO   Figure 7 FlexSPI block diagram   FlexSPI system memory map regions are remapped to different addresses at the FlexSPI sub-module:   Figure 8 FlexSPI memory map FlexSPI can support serial devices compliant with JESD216. Pre-requisites You will need the following Hardware: FRDM-MCXN947 evaluation board. USB C cable. Windows or Linux PC. You will need to install the following Software. MCUXpresso IDE v11.9.0 or above.  FRDM-MCXN947 SDK v2.15.0 or above.  SPSDK and python.     SPSDK installation and virtual environment   We recommend to run the SPSDK on a python virtual environment, as this simplifies the installation of the SPSDK. Before proceeding with installation steps for the SPSDK we recommend to create a folder in your computer. This is where the virtual environment will be running, the SPSDK tools will be called,  and all the files generated by the SPSDK will be stored. Open a terminal, command, or Power Shell prompt  and navigate to your folder and follow the SPSDK installation  commands listed in this guide: Installation Guide — SPSDK documentation            To double check installation of the SPSDK run the following command in your virtual environment. spsdk --version         This figure shows the example of this command and the spsdk version used for this document.   Figure 9 SPSDK version.  Setup  This chapter describes all steps to generate and boot an image from the external memory.  To run the commands listed in this document you will need use your python’s virtual environment. Use the virtual environment you created during SPSDK installation.  PFR settings This section describes the settings that need to be done in the MCX N94x PFR and bootable image.        Create CMPA and CFPA yaml  templates   In the following steps, we are going to focus on editing CMPA area since it contains boot-related fields for external execution.  CFPA area is not required to be edited.            Note:The commands used to generate the templates are based on ‘pfr’ tool  For details on the capabilities of these commands, visit: User Guide - pfr — SPSDK documentation First we are going to use pfr to create our yml CMPA/CFPA templates. These templates contain only the default configurations specified for the CMPA and CFPA areas of  device. If the command run successful the templates will be generated. As shown in figure this figures   Figure 10 Yaml template created.   Edit the CMPA and CFPA yaml templates   Open CMPA   template in any text editor and follow the below steps. Set DEFAULT_BOOT_SOURCE to FLEXSPI_FLASH_XIP_0b01 Set FLEXSPI_AUTO_PROBE   to ENABLE Save the changes in the CMPA template.      Create and write the  CMPA and CFPA binaries         After editing the cmpa yaml, you will generate the CMPA/CFPA binaries from the yml templates.     Import and edit image   This section shows how to create an XIP bootable image from the  MCUXpresso SDK  led_blinky example.    Import the led_blinky demo from the SDK.  Click on “Import SDK example(s)…” (1), then search and select the FRDM-MCXN947 (2), and click “Next” (3). Inside the “SDK import wizard” search and select the “led_blinky  demo (4) and click on “Finish” (5)     Figure 11 Import the blinky example.      Once the demo project is imported open the project properties. Do a right-click in the project’s name (1), then click on “Properties” option (2) and open the project properties(3)   Figure 12 Project ´properties Navigate to the Properties> C/C++ Build > MCU settings section       Figure 13 MCU settings window Make sure that there are two  Flash areas for the external memory: QSPI_FLASH and             QSPI_FCB as shown in Figure 14. If the areas are missing add them as shown in the next step.     Figure 14 External flash areas in the linker.     Add the two flash areas for the  QSPI_FLASH and QSPI_FCB in the “Memory details” table, the move them to the Top.  Click in “Add Flash”  (1) twice, then click on “Move selected memory up in table” (2), the two newly created flash areas should be placed at the top.   Note: Moving a memory area to the top of the “Memory details” table indicates the linker that text and data should be placed preferably in that area. Update the newly created flash areas name and parameters with the ones from the below table.   Type Name Alias Location Size Driver Flash QSPI_FLASH Flash 0x80001000 0xFFFF000 MCXN9xx_SFDP_FlexSPI.cfx Flash QSPI_FCB Flash 2 0x80000400 0x400 MCXN9xx_SFDP_FlexSPI.cfx     Make sure that the flash areas match the ones shown in the Figure 15.     Figure 15 Configured flash areas    Click “Build” (1), once compilation is finished, should return 0 errors (2).   Figure 16 Successfully compiled image.                                      Note: You should see that the QSPI_FLASH section is being used and that the PROGRAM_FLASH section is not. Generate the binary. Navigate to the project’s debug folder and locate generated .axf (1). Then do a right-click in the .axf, and click on Binary utilities > Create Binary.   Figure 17 Create binary.   7 The binary should appear in the debug folder. Get  easily get the binary location by doing a right click on the binary and navigating to  “Show in>System Explorer”   Figure 18 Get created binary with ease. 8. Paste the binary into the workspace where you created the cmpa_bin.bin. This step is only to simplify the commands shown later on.   Erase and ISP mode entry        ISP (In system programming ) is a mode where a host is able to instruct the ROM bootloader to program a new image or the PFR. The which holds the CMPA field with our configuration to do XIP from the external flash memory. Basically, the Host computer sends commands to the ROM bootloader to program the PFR using NXP’s BLHOST. To enter into ISP mode there are two options: ISP pin entry and Debugger mailbox. ISP pin entry requires keeping ISP pin asserted during reset sequence and de-asserting this pin after reset has been completed. Debugger mailbox only requires to use of a SWD debugger to make the ROM entry ISP mode. To enter into ISP mode over ISP pins follow is necessary keep ISP pin asserted during reset sequence and de-assert this pin after reset has been completed. To use the debugger mailbox is only needed having a debugger. For simplicity, the communication protocol will be USB. However, UART can be used as well. Erase the flash memory and enter ISP mode using the nxpdebugmbox. Proceed to run each command nxpdebugmbox erase  nxpdebugmbox ispmode -m 0   This figure shows the expected output when running the two commands from above.   This operation will erase the contents on the internal and external flash memory. Also the PFR contents. Repeating this operation can be useful to get the chip to boot from internal flash memory. Note:  nxpdebugmbox commands need to be run using a SWD-JTAG debugger. For this example on-board debugger of the FRDM-MCXN947 is used. Ping rom Bootloader  Run the following command to ping the rom Bootloader, this way we can ensure that the device was set correctly in ISP mode. blhost  -t 2000 -p COMxxx,115200 -j -- get-property 1     Figure 19 Ping rom Bootloader From now on, an external debugger is not strictly required. The communication with the rom bootloader can be done over UART or USB. For simplicity, the UART protocol-based commands are used from now on in the rest of this document. Write  image and PFR and run demo   We are going to follow the steps to write image.  1 Write CMPA binary. pfr write -p COMxxx,115200 -t cmpa -f mcxn9xx -b cmpa_bin.bin   2 Write CFPA binary. pfr write -p COM140,115200 -t cfpa -f mcxn9xx -b cfpa_bin.bin   3 Provide FlexSPI flash memory configuration blhost  -t 2000 -p COMxxx,115200 -- fill-memory 0x20000000 0x04 0xc0000405   4 Configure and fill memory. blhost  -t 2000 -p COMxxx,115200 -- configure-memory 0x09 0x20000000 blhost  -t 2000 -p COMxxx,115200 -- fill-memory 0x20003000 0x04 0xf000000f   5 Erase flash blhost  -t 2000 -p COMxxx,115200 -- flash-erase-region 0x80000000 0x100000   6 Configure memory. blhost  -t 2000 -p COMxxx,115200 -- configure-memory 0x09 0x20003000    7 Write image. blhost  -t 2000 -p COMxxx,115200 write-memory 0x80001000 frdmmcxn947_led_blinky.bin   8 Reset. blhost  -t 2000 -p COMxxx,115200 reset You might use this command or directly press the reset button from the FRDM board. The below image shows the successful execution of each command. Your FRDM-MCXN947  should be blinking by now. Figure 20 Successful image write and reset. Once the board is reset you will notice that the loaded example will begin to execute.    Double-check execution from external flash    To double-check that the image is executing from the external flash you can use the disassembly view from MCUXpresso. 1  Attach the debugger to the running target and place a breakpoint at any part of the code.   Figure 21 Attach debugger to a running target. Once your debug probe is discovered, click “OK.”   Halt the processor execution. Use the debug button.   Figure 22 halt execution. Reset processor. Use the “Restart button”. The program should be stop at the first line of the main function.   Figure 23 Breakpoint at main. Find and open the disassembly view. Click on “Instruction Stepping Mode” button or search for disassembly. Any option will open the MCUXpresso “Disassembly” view.   Figure 24 Open "Disassembly" view Processor must be running at 0x8000_0000 address space. On the disassembly view you can check that the instructions are executed from address on the range of 0x8000_xxxx which is assigned for external flash.   Figure 25 Running code from external flash. If you want to return the device to run from internal memory, then you need to go back to default values. If there are no modifications, to the ones shown in this document,  to the CMPA and CMPA areas, the nxpdebugmbox command can be executed.      

Abstract   This Knowledge Base text is intended to be an introduction for the MCX A14x/15x Architecture. Therefore, the content that is presented is described in a simplified way.   Contents 1. Introduction  2. Bus and Memory Architecture  3. MCX N vs MCX A series  4. MCXA SoC Power Domain Configuration 5. Clock Tree  6. Life Cycle and ROP State  7. Closing remarks    1.    Introduction   The MCX is the new MCU for NXP generic-purposes microcontrollers. Its portfolio offers a comprehensive selection of Arm® Cortex®-M based MCUs offering expanded scalability with breakthrough product capabilities simplified system design, and a developer-focused experience thought the widely adopted MCUXpresso suite of software and tools. Particularly, the MCXA series MCUs expands the MCX Arm® Cortex®-M33 product offerings with multiple high-speed connectivity, operating up to 96 MHz, serial peripherals, timers, analog and low power consumption. This device has following target applications: Consumer and industrial IoT Industrial Communications Smart Metering Automation and Control Sensors The following figure shows a top-level organization of the modules within the chip organized by functional category. Figure 1. Features block diagram   2.    Bus and Memory Architecture   The memory system of the device includes SRAM, ROM, internal flash, and external memory. The following figure shows the Bus matrix block diagram of this chip. Where there are three bus initiators (CM33, DMA and USB FS) which to access to different slave ports thought a Multilayer AHB bus matrix. ROM, Flash and RAMX0/1 share the same slave port. RAMA0/1 share a second slave port. And the third slave port is used to access to the peripherals.   Figure 2. Bus matrix block diagram   The Bus matrix block diagram has de following features: CM33 Max speed is 96MHz Does not include MPU, FPU, DSP and Trustzone Cache 4KB LPCAC on CM33 code bus 8-way, 2-set-associative design based on 256-byte superpages. The access to flash can be cached. Write through Flash Up to 128KB flash. Line buffer and prefetch buffer IFR0 sector0 is CMPA region Memory Block Checker (MBC) is used to control the access permission Swap RAM SRAM is divided into Code TCM and System TCM: CTCM: Mapped to CM33 code bus space RAM X0: 8 KB 32-bit RAM RAM X1: 4 KB 32-bit RAM Can only be used as code RAM when LPCAC is disabled. STCM: Mapped to CM33 system bus space: RAM A0: 8 KB 32+7-bit ECC RAM RAM A1: 16 KB 32bit RAM Execute permission is configurable Remap When remap is enabled, the access to RAM X0, will be remapped to the end of system RAM   3.    MCX N vs MCX A series   The MCX N series have feature-rich on-chip accelerators and peripheral sets. Aimed at applications that need higher performance and fast features. The MCX A series have several device options for a wide range of applications. Provides coverage for all applications requiring microcontrollers in entry-level target products. The following table summarizes the main features of the MCX A and the MCX N series to compare their differences. Table 1. Feature Comparison between MCX N and MCX A series Description MCXN94x MCXA14x/15x Comments System 2x DMA3, CRC, 2x WWDT, SPC, SCG, EIM, ERM, INTM, EWM, SYSCON, WUU, CMC, VBAT 1x DMA3, CRC, WWDT, SPC, SCG, CMC, VBAT, EIM, ERM, SYSCON, WUU - MRCC in MCXA SYSCON is used to control peripherals’ clock select, clock divider and clock gating. - SPC and SCG programming model is forward compatible with MCXN. Security S50, PKC, PUF, TRNG, SM3, 2x GDET, Tamper, eFuse, ITRC, 2x CDOG, LVD/HVD, ROP (Read out protection), 1x CDOG, GLIKEY   Clocking 2x PLL, FRO144M, FRO12M, OSC48M, OSC32K, FRO16K FRO192, FRO12M, OSC48M, FRO16K - OSC48M min. frequency is reduced to 8MHz. Communications USB FS, 10x LP_FLEXCOMM,  2x FlexCAN, 2x SAI, 2x I3C, FlexIO, 2x EMVSIM USB FS, 2x LPSPI, 3x LPUART, LPI2C, I3C - LPSPI/LPUART/LPI2C are compatible with LP_FLEXCOMM. FIFO depth in MCXA is 4, and MCXN is 8. - I3C is new version in MCXA. It is compatible with MCXN - USB FS doesn’t support USB DCD in MCXA. High Speed Interface USB HS, FlexSPI, SDHC, ENET, eSPI, SPI Filter LPSPI (LP_FlexCOMM) LPSPI   Timers 2x FlexPWM, 2x QDC, 5x Ctimer, SCT, uTimer, OS Timer, RTC, 2x LPTMR, MRT 1x FlexPWM, 1x QDC, 3x Ctimer, SCT, uTimer, OS Timer, Wakeup Timer,  LPTMR - FlexPWM and Ctimer support up to 192MHz clock - 3 Sub Modules in FlexPWM of MCXA - QDC is a new design, but compatible with MCXN Analog 2x 16bit ADC, 3x DAC, 3x CMP, 3x OPAMP, VREF, TSI 1x 12bit ADC, 2x CMP - The ADC MCXA is single ended ADC, with single sample/hold circuit. Supports up to 4Msps in 12bit mode. Regulators DCDC, SYS_LDO, CORE_LDO, VBAT, SRAM_LDO OD/SD/MD RUN Mode CORE_LDO, SRAM_RET_LDO   Power Mode RUN Mode: OD/SD/MD LP Mode: Sleep/DS/PD/DPD/VBAT RUN Mode: SD/MD LP Mode: Sleep/DS/PD/DPD   IO 6 rails, 124 GPIO, 100M/50M/25M IO 2 rails, ~52 GPIO, 50M/25M IO High Drive IO, 5V Tolerant IO   NEW MODIFIED       New and modified features are highlighted. And as it can be seen, most of the features of the MCX A are compatible with the MCX N.   4.    MCXA SoC Power domain configuration   The following figure introduce in a simplified way the Power Architecture block diagram of the MCX A. Where it can be seen that consist in three power supplies (VDD, VDD_ANA and VDD_USB) to power system and peripherals.   Figure 3. Power Architecture   VDD is the main supply which powers SYSTEM Domain, PMC, LDO_CORE and IO. At the same time CORE_MAIN Domain is supplied by LDO_CORE. VDD_ANA supplies ADC. And VDD_USB supplies USB FS PHY. Power Architecture has the following features: Run Mode SD mode with 1.1V VDD_CORE, 96MHz max. MD mode with 1.0V VDD_CORE, 48MHz max. Low Power Mode Sleep Mode DS Mode PD Mode CORE_MAIN domain and RAM are retained in different voltage DPD Mode. CMC and SPC control the LP mode, which is compatible with MCX N RAM Retention 3 RAM retention groups, which can be retained independently RAM X0 and RAM X1 RAM A0 RAM A1 All RAM can be retained down to DPD mode RAM retention control logic is implemented in SPC Power Sequence VDD and VDD_ANA must be ramp up same time with same level Voltage Monitors POR on VDD LVD and HVD on VDD LVD on VDD_CORE VDD_USB detector The following figure shows the Power Mode Transition block diagram. After POR the chip enters in Reset, when it exits from Reset the chip enters Active Mode. By performing Active Mode, it is able to enter all Low Power Modes. In Sleep and Deep Sleep Modes, it is possible to return directly to Active Mode. Meanwhile, to exit from Deep Power Down Mode, a Reset must be performed. Figure 4. Power Modes Transition   5.    Clock Tree   The following Figure shows a high level of Clock Architecture block diagram. In the left of the block diagram there are the on-chip clock sources, meanwhile in the right there is the distribution of the clock signals that clocking the systems and peripherals of the chip. The SCG controls FRO192M, FRO12M and SOSC clock sources. VBAT implements the 16 kHz internal clock source. And the MRCC provides on-chip modules their own dedicated MRCC bits for clock gating, reset control and configuration options. Figure 5. Clock Architecture The Clock Architecture has the following features: Clock Source FRO192M. Outputs 192/96/48MHz FRO12M. Outputs 12MHz and 1MHz. SOSC. Supports 8~50MHz FRO16K. Output 16.384KHz Clock Management Overall clock architecture is same with MCXN SCG and VBAT control clock generators MRCC in SYSCON controls clock mux and clock divider of the system and peripherals.   6.    Life Cycle and ROP State The following Table summarizes the Life Cycle State model and the Read Out Protection (ROP), which are designed to protect customer code and data from reading from the device internal flash. There are different levels of protection in the system, so that access to the on-chip flash and use of ISP can be restricted. Also, the life cycle state of the device determines the debug access and ISP command availability. Table 2. Life Cycle and ROP Life Cycle State ROP State Debug Port Status Debug Mail Box Command ISP Command NXP_PROVISIONED OEM_OPEN OEM_FIELD_RETURN NXP_FIELD_RETURN ROP0  ROP_STATE = 0xFFFF_FFFF  ROP_STATE_DP = 0xFFFF_FFFF - Disabled by default - Enabled by Bootloader Full command OEM_CLOSED ROP1    ROP_STATE = 0x0000_0003    ROP_STATE_DP = 0x0000_0003 - Disabled by default - Not enabled by Bootloader - Debug configure register is not locked Reduced command ROP2    ROP_STATE = 0x0000_0001    ROP_STATE_DP = 0x0000_0001 - Disabled by default - Not enabled by Bootloader - Debug configure register is locked Reduced command OEM_NO_RETURN ROP3    ROP_STATE = 0x0000_0000    ROP_STATE_DP = 0x0000_0000 - Disabled by default - Not enabled by Bootloader - Debug configure register is locked No command BRICKED Other value - Disabled by default - Not enabled by Bootloader - Debug configure register is locked No command   NXP_BLANK and NXP_FAB are NXP states that are not available for customers. NXP_PROVISIONED, OEM_OPEN, OEM_FIELD_RETURN and NXP_FIELD_RETURN are initial customer development states after leaving NXP manufacturing. OEM_CLOSED is the customer in-field application state, with ROP protection. OEM_NO_RETURN is the customer in-field application state, with ROP protection which prevents use of field return. And finally, BRICKED is the end-of-life state to prevent device use.   7.    Closing remarks   The MCX A series is based on the Arm Cortex-M33 operating at up to 96 MHz. It is scalable and easily migrated between N and A series given that peripherals and memories are very similar. The main on-chip memories are a Non-Volatile Flash memory with ECC and a RAM with ECC and Self-Test. Enhanced peripherals are designed with specific use cases in mind. This gives the applications a lot of focus on what they need. Improved Read Out Protection is built into the hardware designed to protect customer code and data from unauthorized readings. This device provide great flexibility and multiple options for the user to achieve low-power consumption with memory retention. Comprehensive serial communications included in the MCX A allow to interact with various components in customer applications. The analog integration selection within the MCX A also provides real-time response to the outside world, including ADC, CMP and temperature sensor. Utilize MCUXpresso software and tools to optimize, ease and help accelerate your embedded system development with a development suite that includes device configuration tools, drivers and middleware, multiple IDEs and a secure provisioning tool.