fsl_sd.c issue

[mspenard603]

Hi All,

 I'm trying to incorporate SD-card support, based on the SDK's fatfs example, into my own project.

I have the pins and clock plumbed without conflict. And card detection works. However, whenever I try and format the card ( using f_mkfs() ), or do any write operation really, things get hung up.

f_mkfs() calls SD_Write() in fsl_sd.c which then goes to check status but never returns. What would cause this?

/* Wait for the card's buffer to be not full to write to improve the write performance. */
while ((GET_SDMMCHOST_STATUS(card->host.base) & CARD_DATA0_STATUS_MASK) != CARD_DATA0_NOT_BUSY)
{
}

[ZhangJennie]

Hi

Please let us know your chip part number. Thus we can have the right engineer to check your issue. Thanks.

Jun Zhang

[mspenard603]

iMXRT1062.

I tracked it down. Despite having pin_mux and clock .c files setup right the clocking was still off. This is because in the SDK example there's a #define in board.c that sets the PFD source. 

Defaults:

//#define BOARD_USDHC1_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U))
//#define BOARD_USDHC2_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / (CLOCK_GetDiv(kCLOCK_Usdhc2Div) + 1U))

SDK example requires:

#define BOARD_USDHC1_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U)) // mls from SDK example
#define BOARD_USDHC2_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(kCLOCK_Usdhc2Div) + 1U)) // mls from SDK example

This is very confusing because the main example source sets it up with pdf0 and yet even there it is commented as pdf2 !?

void BOARD_InitSDcardClock(void)
{
/*configure system pll PFD2 fractional divider to 18*/
CLOCK_InitSysPfd(kCLOCK_Pfd0, 0x12U);
/* Configure USDHC clock source and divider */
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 0U);
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1U);
}

What is going on here?!

[jorge_a_vazquez]

Hi Mike Spenard

Sorry for the late response, this is an error in the example code and the configuration used for the board file. Please check the following post:

About Max Frequency of USDHC

Have a great day,
TIC

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[mspenard603]

Thanks Jorge for that link. I've set my project up as the link suggested:

• /* Init System pfd0. */

  CLOCK_InitSysPfd(kCLOCK_Pfd0, 16);

  /* Set USDHC1_PODF. */

  CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2);

  /* Set Usdhc1 clock source. */

  CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1);

• Change the definition of BOARD_SD_HOST_SUPPORT_SDR 104 _ FREQ on board.h as follows.

  #define BOARD_SD_HOST_SUPPORT_SDR104_FREQ (198000000U)

However, I'm still getting erratic behavior from the SDcard bus. Reads go crazy with high ascii garbage occasionally. And sometimes with parts of a file going missing. ChaN FatFS isnt returning any errors, so I has to be getting garbage to start with.

Am I still suppose to be setting up board.h with the following?

#define BOARD_USDHC1_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U)) // mls from SDK example
#define BOARD_USDHC2_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(kCLOCK_Usdhc2Div) + 1U)) // mls from SDK example

[mspenard603]

Oh, just noticed my card, while it is a SDHC is not a UHS-I. Is there a way to configure the clocking to work with any available SDHC?!

[jorge_a_vazquez]

Hi Mike Spenard

Using the correct clock source for the module, then the driver would take that clock and div and multiply it for the needed clock speed. The Reference MAnual Mentioned that the uSDHC module only supports:

SD/SDIO UHS-I mode(up to 208 MHz in SDR mode, up to 50 MHz in DDR mode)

Best regards

Jorge Alcala

[mspenard603]

Well the correct clock sourcing is not clear to me which is why I ask.The example code in board.c uses Pfd0 "CLOCK_InitSysPfd(kCLOCK_Pfd0, 16);" while the board.h uses Pdf2 "#define BOARD_USDHC1_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U)) "

This doesn't make sense to me and seems incorrect.What are the correct settings for board.c and board.h?

Thank you,

 /ms

[jorge_a_vazquez]

Hi Mike

Yes, as you mentioned, there is an error in the example code, it is incorrect to select Pfd0 clock and actually get the clock of the fdp2 to config the module. you could use the settings used by the example:

static void BOARD_USDHCClockConfiguration(void)
{
    /*configure system pll PFD0 fractional divider to 18 pfd0 = 528MHz */
    CLOCK_InitSysPfd(kCLOCK_Pfd0, 18U);
    /* Configure USDHC clock source and divider 528 / 1 = 528MHz */
    CLOCK_SetDiv(kCLOCK_Usdhc1Div, 0U);
    CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1U);
}
‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

and change the line in the board.h file as:

#define BOARD_USDHC1_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U))‍‍

Hope this could help you.

Regards

Jorge Alcala

[mspenard603]

Thank you. The SDcard is detected and I can mount FatFS. But only if I press the reset button. If I do a flash or enter debug mode the SD card is detected but FatFS is unable to mount. For some reason it seems to need a cold power cycle. Any thoughts on how to fix this so I can run debug mode?

[jorge_a_vazquez]

Hi Mike Spenard

Sorry for the late response, but I'm not able to reproduce the issue that you are seeing. I'm using an 8GB HC 1 memory. Your issue could be related to a big deviation of the clock from the ideal clock that you need, as you know, depending on the sd card technology you need a frequency, and you may have a big deviation with the card that you use.

https://www.sdcard.org/press/past_evens/pdf/SD_Standards_and_Technology_GWTaipei_Oct2014.pdf 

Regards

[mspenard603]

No worries, I traced the f_mount() issue down to a difference between NXP's eval board and EmbeddedArtists'. I was unaware that SD_Reset is on a different pin with EmbArt's RT1062 board. What is confusing is getting this sd_reset pin mapping wrong presents itself as a check_fs() FAT signature-block mismatch error within f_mount().

[ZhangJennie]

Thanks. Our iMXRT support will check your issue.