SDK example code and issue with flexspi DLL lock (using hyperflash)

[mimlo]

Hi,

I have a question regarding interfacing HYPERFLASH memory with flexspi controller on imxrt1170 microcontroller.

My project utilizes code which was ported from evkbimxrt1050_flexspi_hyper_flash_polling_transfer project to work with imxrt1170 microcontroller. We use custom hardware with imxrt1170 uc and hyperflash S26HS512T from Infineon. The hardware connections to the hyperflash memory were made exactly the same as in the EVAL board MIMXRT1050-EVKB.
Since I'm using S26HS512T with 1.8VCC hyperflash memory from Infineon, I need it to run with differential master clock. Flexspi API provides config structure called flexspi_config_t which has the following bit set to true in my code:
enableSckBDiffOpt (It enables the second clock for the flash memory as far as I understand it correctly)

By far I was able to read SFDP header bytes, which confirms that the communication between flexspi<=>hyperflash works correctly provided  that flexspi root clock is less than 100MHz(DLL loop is disabled). When flexspi root clock is set above 100MHz, it results in the code being stuck in the code below:

/* Wait slave delay line locked and slave reference delay line locked. */
while ((base->STS2 & statusValue) != statusValue)
{
}

The questions are as follows:
1.) Now to my question, What is the meaning of isSck2Enabled in the flexspi_device_config_t  struct and should I set it to true in order to utilize differential master clock mode?

When this bit is set, DLL calibration is disabled (according to the flexspi FLEXSPI_UpdateDllValue() function logic).

2.) Should I use DLL calibration at all, when using differential master clock for my hyperflash memory?

Thanks,
Michael

[RaRo · Accepted solution]

Hello @mimlo,

First of all, we apologize for the delay.

enableSckBDiffOpt according to i.MX RT1170 Processor Reference Manual is a bit used to set Differential clock to A_SCLK.

[Chapter 30. FlexSPI Controller (FLEXSPI). Section 30.7.2.4.4. Fields]

Meanwhile, isSck2Enabled could enable the B_SCLK pad, this might be used when you are not using the combination mode, meaning that you may want to use both SCLK (Port A and Port B).

Regarding your questions about DLL, we recommend you continue using the FLEXSPI_UpdateDllValue() function, as it is part of the example to work with Hyper Flash.

Finally, relating to the root clock, may be useful to take a look to i.MX RT1170 Processor Reference Manual. Section 30.3.17.5. DLL configuration for sampling. There it is mentioned the proper workarounds to work with it.

Best regards, Raul.

[mimlo]

Thanks for the reply.

In my case, we use the COMBINE mode for FLEXSPI1 which uses 8 data signals (A_DATA_0 - A_DATA_3 | B_DATA_0 - B_DATA_3). Furthermore, we use 2 pins to properly clock the memory in differential mode.
From what I understand:
    -enableSckBDiffOpt configures the B_SCLK to work as a negation of the A_SCLK clock which enables the differential clock for the memory.
    -isSck2Enabled is used to sort of separate the 2 clocks from each other in order to be able to supply the SCLK_B clock to some other flash chip memory.

Summing that up, for my case, I should not be setting the isSck2Enabled to 1 (as I only use 1 external memory and I need it to run with differential clock) and only be setting enableSckBDiffOpt  to 1.

Is my understanding correct?

BR,
Michael

[RaRo]

Hello @mimlo,

As you mention, please not modify isSck2Enabled to run with differential clock.

Best regards, Raul.

[mimlo]

Thank you for clarification.

BR,
Michael