Hi Bin,
You know the wrong operation on internal regulator and power gating may damage the chips, so the power library is in binary format.
That might make some sense, but this limits the use of the power.lib to compiler environments provided by NXP.
Not having the power.lib source code means that I need to write some functions myself and that only makes the chance of making mistakes bigger ...
I just noticed the new release of the user manual (Rev 1.2 - 24 February 2017) contains a separate chapter for the power control API.
By the way; it looks strange to see that the drivers do mange the power configuration but don't enable the clocks themselves. Do you know of any reason why this is done this way?
I may not understand fully, can you have an example?
I noticed this while working on the PLL. fsl_clock.c and fsl_utick.c have some functions that control the power themselves. But apparently only those files do this.
As an example:
| fsl_clock.c: |
|---|
pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup) { /* Enable power VD3 for PLLs */ POWER_SetPLL(); /* Power off PLL during setup changes */ POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0); /* Write PLL setup data */ ... /* Flags for lock or power on */ if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0) { ... /* Enable peripheral states by setting low */ SYSCON->PDRUNCFGCLR[0] = SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK; } ... return kStatus_PLL_Success; } |
The function begins with POWER_SetPLL() and POWER_EnablePD() to enable Vd3 to the PLLs and disabling power to the system PLL, then it programs the PLL and enables the power by writing directly to PDRUNCFGCLR[0].
Apart from the fact that two different methods are used to write to bit 22 in PDRUNCFG (first by calling POWER_EnablePD() and later by writing to PDRUNCFGCLR) this does make sense to prevent eratic power behavior due to CCO jitter.
But if I want to use the ADC, I need to clear the respective bits in SYSCON->PDRUNCFG[0] myself before using the ADC.
As a side note, the SYSCON_PDRUNCFG_PDEN_SYS_PLL_... defines are strange:
| LPC54608.h |
|---|
#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK (0x400000U) #define SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT (22U) #define SYSCON_PDRUNCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << \
SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK) |
The 0x400000 must always match 1<<22.
I found more of those little bits but I think it's best to leave these as-is and wait for the new SDK release.
For the new release, as a user, I ever got a mail for that
Good to know. I am a front line developer and working with new chips means that it takes time to get the development boards, chip samples, documentation and programming tools.
It's good to see that NXP is focussing on this too. Updates on user manual and SDK are highly appreciated :smileyhappy:
Regards,
Rob