I'm using FreeRTOS Kernel V10.0.1 which was the latest version when the code development started (last year)
It looks like the developer who wrote the original code for the project, may have made a mistake with the core clock frequency, as the board is fed by an external clock frequency of 12.288Mhz instead of 8Mhz, and I can't see anything different in the clock configuration to compensate for this.
Because of this custom frequency is required for synchronization with specialist data decode IC's, I thought the decision was made to slightly overclock the core frequency to 122.88Mhz, but when I call
CLOCK_GetFreq(kCLOCK_CoreSysClk)
its showing 184.32Mhz
So either that function is not returning the correct value, because the definitions being incorrect, or it is correct and the processor is being accidentally overclocked.
I'm trying to contact the previous developer, but he's not replied yet.
So I think I'm going to have to check all the PLL and divider settings.
I'm now trying to find a example calculation for how to set the MCG PLL to 10 or possibly 8 instead of 15