Can't debug code link to RAM with Jlink

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Can't debug code link to RAM with Jlink

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h_bouchard
Contributor III

I am using the rt1064 on a custom board (SDK version 2.9.1) and debugging using MCUXpresso IDE v11.3.0. I would like to link application to RAM but I'm not able to debug with Segger JLink Ultra+ probe.

To accomplish this, I did the following:

  • Set up SRAM_ITC to be the first RAM region listed in the memory configuration table (this region is large enough to hold our application).
  • Set up the SRAM_DTC to placed the heap and stack there.
  • Checked the "Link application to RAM" checkbox in the managed linker script.
  • In the Startup tab of the 'Edit Launch Configuration' dialog, set "monitor reset 6" to "Initialization Commands".
  • Remove XIP from SDK setup.
  • Remove XIP preprocessor defines from project settings.

When I try to download this through the debugger, the behavior is not stable. The first time I get this:

 

Spoiler

[26-2-2021 06:00:41] Executing Server: "C:\Program Files (x86)\SEGGER\JLink\JLinkGDBServerCL.exe" -nosilent -swoport 2332 -select USB=504505558 -telnetport 2333 -endian little -ir -speed auto -port 2331 -vd -device MIMXRT1064xxx6A -if SWD -halt -reportuseraction
SEGGER J-Link GDB Server V6.88c Command Line Version

JLinkARM.dll V6.88c (DLL compiled Dec 4 2020 18:05:56)

Command line: -nosilent -swoport 2332 -select USB=504505558 -telnetport 2333 -endian little -ir -speed auto -port 2331 -vd -device MIMXRT1064xxx6A -if SWD -halt -reportuseraction
-----GDB Server start settings-----
GDBInit file: none
GDB Server Listening port: 2331
SWO raw output listening port: 2332
Terminal I/O port: 2333
Accept remote connection: localhost only
Generate logfile: off
Verify download: on
Init regs on start: on
Silent mode: off
Single run mode: off
Target connection timeout: 0 ms
------J-Link related settings------
J-Link Host interface: USB
J-Link script: none
J-Link settings file: none
------Target related settings------
Target device: MIMXRT1064xxx6A
Target interface: SWD
Target interface speed: auto
Target endian: little

Connecting to J-Link...
J-Link is connected.
Device "MIMXRT1064XXX6A" selected.
Firmware: J-Link Ultra V4 compiled Nov 12 2020 10:07:39
Hardware: V4.00
S/N: 504505558
Feature(s): RDI, FlashBP, FlashDL, JFlash, GDB
Checking target voltage...
Target voltage: 3.30 V
Listening on TCP/IP port 2331
Connecting to target...
InitTarget() start
InitTarget()
_TargetHalt: CPU halted
InitTarget() end
Found SW-DP with ID 0x0BD11477
DPIDR: 0x0BD11477
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x04770041)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FD000
CPUID register: 0x411FC271. Implementer code: 0x41 (ARM)
Found Cortex-M7 r1p1, Little endian.
FPUnit: 8 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ E00FD000
ROMTbl[0][0]: E00FE000, CID: B105100D, PID: 000BB4C8 ROM Table
ROMTbl[1] @ E00FE000
ROMTbl[1][0]: E00FF000, CID: B105100D, PID: 000BB4C7 ROM Table
ROMTbl[2] @ E00FF000
ROMTbl[2][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS-M7
ROMTbl[2][1]: E0001000, CID: B105E00D, PID: 000BB002 DWT
ROMTbl[2][2]: E0002000, CID: B105E00D, PID: 000BB00E FPB-M7
ROMTbl[2][3]: E0000000, CID: B105E00D, PID: 000BB001 ITM
ROMTbl[1][1]: E0041000, CID: B105900D, PID: 001BB975 ETM-M7
ROMTbl[1][2]: E0042000, CID: B105900D, PID: 004BB906 CTI
ROMTbl[0][1]: E0040000, CID: B105900D, PID: 000BB9A9 TPIU-M7
ROMTbl[0][2]: E0043000, CID: B105F00D, PID: 001BB101 TSG
Cache: Separate I- and D-cache.

I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
InitTarget() start
InitTarget()
_TargetHalt: CPU halted
InitTarget() end
Found SW-DP with ID 0x0BD11477
DPIDR: 0x0BD11477
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FD000
CPUID register: 0x411FC271. Implementer code: 0x41 (ARM)
Found Cortex-M7 r1p1, Little endian.
FPUnit: 8 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ E00FD000
ROMTbl[0][0]: E00FE000, CID: B105100D, PID: 000BB4C8 ROM Table
ROMTbl[1] @ E00FE000
ROMTbl[1][0]: E00FF000, CID: B105100D, PID: 000BB4C7 ROM Table
ROMTbl[2] @ E00FF000
ROMTbl[2][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS-M7
ROMTbl[2][1]: E0001000, CID: B105E00D, PID: 000BB002 DWT
ROMTbl[2][2]: E0002000, CID: B105E00D, PID: 000BB00E FPB-M7
ROMTbl[2][3]: E0000000, CID: B105E00D, PID: 000BB001 ITM
ROMTbl[1][1]: E0041000, CID: B105900D, PID: 001BB975 ETM-M7
ROMTbl[1][2]: E0042000, CID: B105900D, PID: 004BB906 CTI
ROMTbl[0][1]: E0040000, CID: B105900D, PID: 000BB9A9 TPIU-M7
ROMTbl[0][2]: E0043000, CID: B105F00D, PID: 001BB101 TSG
Cache: Separate I- and D-cache.

I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
Connected to target
Waiting for GDB connection...Connected to 127.0.0.1
Reading all registers
Read 4 bytes @ address 0x00000000 (Data = 0x00000000)
Read 4 bytes @ address 0x00000000 (Data = 0x00000000)
Read 4 bytes @ address 0x00000000 (Data = 0x00000000)
Connected to 127.0.0.1
Reading all registers
Read 4 bytes @ address 0x00000000 (Data = 0x00000000)
Read 4 bytes @ address 0x00000000 (Data = 0x00000000)
Read 4 bytes @ address 0x00000000 (Data = 0x00000000)
GDB closed TCP/IP connection (Socket 1056)
GDB closed TCP/IP connection (Socket 1064)

Server has been shut down.

But the second time I try to debug I get this:

 

 

Spoiler

C:
xp\MCUXpressoIDE_11.3.0_5222\ide\plugins\com.nxp.mcuxpresso.tools.win32_11.3.0.202008311133 oolsinrm-none-eabi-gdb.exe: warning: Couldn't determine a path for the index cache directory.
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Type "show copying" and "show warranty" for details.
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Type "show configuration" for configuration details.
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The question is, am I missing any settings?

Thanks for your help!

Hugo

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1 Solution
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jingpan
NXP TechSupport
NXP TechSupport

Hi h_bouchard,

I made a example which use jlink and run in sram. Please take a try.

 

Regards,

Jing 

View solution in original post

5 Replies
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nickwallis
Contributor IV

Hi,

You need to modify the debugger connect script (.SCP file) to reflect the changed flexRAM configuration. Did you do that?

-Nick

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h_bouchard
Contributor III

Hi Nick,

Thanks for the reply but the flexRAM setting hasn't change therefore no need to modify .scp file.

Hugo

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167 Views
jingpan
NXP TechSupport
NXP TechSupport

Hi h_bouchard,

I made a example which use jlink and run in sram. Please take a try.

 

Regards,

Jing 

View solution in original post

157 Views
h_bouchard
Contributor III

Hello Jing,

Thank you so much for your help!!

As I expected, it was a debug configuration problem. The Initialize CPU registers checkbox was checked. Once unchecked, it worked fine.

Your the best !

Hugo

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h_bouchard
Contributor III

I just tried with Ozone (Segger GUI for debugging) and I managed to start debugging my application. So the code is link to RAM properly.

It is most likely a faulty debug configuration. Does someone has managed to debug an application link to RAM with a JLink probe and MCUXpresso?

Thanks
Hugo

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