I need some troubleshooting ideas.
I have a custom board with K82, SDK2.8.0, MCUXresso IDE v11.7.1_9221, Segger J-Link Compact. There's a debug console on LPUART4.
Execution fails before hitting initial breakpoint. Debugger opens view on startup_mk82f25615.c:

If I hit pause:

If I then disconnect J-Link and power cycle the board it still does not run (my LED heartbeat indicator is dead).
If I then load the .bin file with J-Link Commander (V7.86e), I get:
J-Link>loadbin C:\Projects\sspm-cl-v1\DTE_L2\sspm-cl-v1.bin 0
'loadbin': Performing implicit reset & halt of MCU.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
Reset: SYSRESETREQ has confused core.
Found SW-DP with ID 0x2BA01477
DPIDR: 0x2BA01477
CoreSight SoC-400 or earlier
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Skipped. Could not read CPUID register
Attach to CPU failed. Executing connect under reset.
DPIDR: 0x2BA01477
CoreSight SoC-400 or earlier
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Skipped. Could not read CPUID register
Could not find core in Coresight setup
Reset: Using fallback: VECTRESET.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.VECTRESET.
Reset: VECTRESET has confused core.
Reset: Using fallback: Reset pin.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via reset pin
Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Reset: Reconnecting and manually halting CPU.
Found SW-DP with ID 0x2BA01477
DPIDR: 0x2BA01477
CoreSight SoC-400 or earlier
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Skipped. Could not read CPUID register
Attach to CPU failed. Executing connect under reset.
DPIDR: 0x2BA01477
CoreSight SoC-400 or earlier
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Skipped. Could not read CPUID register
Could not find core in Coresight setup
T-bit of XPSR is 0 but should be 1. Changed to 1.
AfterResetTarget()
Downloading file [C:\Projects\sspm-cl-v1\DTE_L2\sspm-cl-v1.bin]...
HandleBeforeFlashProg() start
HandleBeforeFlashProg() end - Took 4us
****** Error: Failed to preserve target RAM @ 0x1FFF0000-0x2002FFFF.
Failed to prepare for programming.
Unspecified error -1
J-Link>