Hi Cedric,
I have checked the implementation and it seems that there are selected confusing names of the divider and multiplier only. The clock model works properly.
If you look into reference manual (UM11060) you can find the following expression for computing the FRG clock:
Flexcomm Interface function clock = (clock selected via FRGCLKSEL) / (1 + MULT / DIV)
And also the following definition of the related bitfields:
It is mean that the MULT bitfield works as the divider and DIV bitfield works as the multiplier part of the fractional divider.
In the clock model (clock diagram) the FRGCTRL_MUL multiplier controls the DIV bitfield and must be 0xFF. The FRGCTRL_DIV divider controls the MULT bitfield (1+MULT/0xFF = (0xFF + MULT) / 0xFF), i.e. the divider provides values 256 - 511.
It means that the clock model works properly and provide the correct values in the FRGCTRL register (you can also check the bitfield values in the Registers window of the Clocks tool).
Best Regards,
Marek Neuzil
Hi Cedric,
I have checked the implementation and it seems that there are selected confusing names of the divider and multiplier only. The clock model works properly.
If you look into reference manual (UM11060) you can find the following expression for computing the FRG clock:
Flexcomm Interface function clock = (clock selected via FRGCLKSEL) / (1 + MULT / DIV)
And also the following definition of the related bitfields:
It is mean that the MULT bitfield works as the divider and DIV bitfield works as the multiplier part of the fractional divider.
In the clock model (clock diagram) the FRGCTRL_MUL multiplier controls the DIV bitfield and must be 0xFF. The FRGCTRL_DIV divider controls the MULT bitfield (1+MULT/0xFF = (0xFF + MULT) / 0xFF), i.e. the divider provides values 256 - 511.
It means that the clock model works properly and provide the correct values in the FRGCTRL register (you can also check the bitfield values in the Registers window of the Clocks tool).
Best Regards,
Marek Neuzil
