USB PLL setup values do not match

[rex_lam]

After using the clock config tool on OM13098 dev board (LPC546xx), I got the following values for USB PLL.

    /*!< Set up USB PLL */
    const usb_pll_setup_t usb_pllSetup = {
        .msel = 15U,
        .nsel = 0U,
        .psel = 0U,
        .direct = false,
        .bypass = false,
        .fbsel = false,
        .inputRate = 12000000U,
    };
    CLOCK_SetUsbPLLFreq(&usb_pllSetup);                        /*!< Configure PLL to the desired value */

I expected these values to match the ones in CLOCK_EnableUsbhs0HostClock() in fsl_clock.c but they don't. Here are the values from CLOCK_EnableUsbhs0HostClock():

        usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U };

        CLOCK_SetUsbPLLFreq(&pll_setup);

Can I trust the values from the clock config tool? Is there a reason to use USB_N_DIV of 4 and USB_M_MULT of 64 in CLOCK_EnableUsbhs0HostClock()? Any advice would be greatly appreciated.

[padraig_fogarty]

I noted the same discrepancy between the clock config tool and the source in fsl_clock.c.

Although both sets of figures may arrive at the same output clock frequency, the concern I have is that the settings in fsl_clock.c appear to set the USB PLL beyond the recommended MAX frequency in the datasheet.

So I'd like to know if it is safe to use the fsl_clock.c setting function, or do I have to implement my own copy using the values from the clock config tool?

[rex_lam]

Based on the formula Fout = M*(Fin/N)/(2*P), the USB PLL is not set beyond the recommended MAX frequency (using the values in fsl_clock.c). This is what it looks like in the clock tool.

So it should be safe to use fsl_clock.c functions.

[padraig_fogarty]

Okay, yes I see that I missed the fact that the order of the psel and nsel figures is different in the auto generated code.

Thanks

[jeremyzhou]

Hi Rex Lam,

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
According the formula, Fout = M*(Fin/N)/(2*P), Fcco = M * (Fin/N) , when  usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U };,
it's easy to get USB clock = 64*(12 MHz/2)/(2*4)= 48 MHz.
About the structure usb_pllSetup that clock config tool generates, I can't jump to the conclusion that the structure is wrong before I can get more information, so I was wondering if you share the screenshot of the clock config tool.
Have a great day,
TIC

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[rex_lam]

Jeremy,

Thank you for your quick response. In usb_pll_setup_t, the second field is actually psel, and the third field nsel. Therefore, the formula is

64*(12 MHz/4)/(2*2) = 48 MHz

I have attached my clock diagram. I hope this is what you are asking for. I think the final frequencies are correct, but I would like to understand why it is different than the values used in fsl_clock.c.

Rex

[jeremyzhou · Accepted solution]

Hi Rex Lam,

Thanks for your reply.
It's Okay to select a different set of Pre-divider, Feedback-divider and Post-diver to output 48 or 96 MHz, the usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U }; just is a template.
Hope this is clear.
Have a great day,
TIC

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[rex_lam]

Thank you Jeremy. Much appreciated.