RT1021 -- blhost to query flash ID to enable the coresponding QE bit

JamesNgo · ‎09-22-2023

My RT1021 based design supports several compatible spiFlash types and vendors. Each of these flash parts has the QE bit at different position, apparently shown below:

Questions:

1. BLHOST does not seem to have a command or method to query the flash parts ID/vendor to configure Quad Enable bit appropriately. It appears it is OK under the assumption that the system design supports 1 flash type at a time. If different part is used in the system, BLHOST scripts have to be changed to work with a different part. Please confirm this.

2. Given (1) is true, is there any option to query the flash part ID (during runtime) to enable the QE bit appropriately for design that supports multiple compatible flash parts?

Thanks

-james

JamesNgo · ‎09-29-2023

Hi Pavel,

I couldn't generate the IVT_flashloader.bin as I described earlier due to the unknown reason it couldn't read the input file.bin. So I explored other options...

And I found one working option that I'd like to share the findings to benefit all other fellows here who may be interested.

Technically the IVT has the boot info that the SPDHOST needs to "jump". I managed to INCLUDE the entire IVT into the flashloader.bin on the top image in the code (as if elftosb would have worked) -- hence I do NOT have to use the "elftosb" to generate it.

Preprocessor:

XIP_BOOT_HEADER_DCD_ENABLE=1
XIP_BOOT_HEADER_ENABLE = 1

linker.icf

define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0;
define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0;

define symbol m_interrupts_ram_start = 0x20000000;
define symbol m_interrupts_ram_end = 0x20000000 + __ram_vector_table_offset__;

define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__;
define symbol m_data_end = 0x2000FFFF;

define symbol m_data2_start = 0x20200000;
define symbol m_data2_end = 0x20207FFF;

define symbol m_interrupts_start = 0x2020A000;
define symbol m_interrupts_end = 0x2020A3FF;
define symbol m_text_start = 0x2020A400;
define symbol m_text_end = 0x2021FFFF;

define exported symbol m_boot_hdr_conf_start = 0x20208000;
define symbol m_boot_hdr_ivt_start = 0x20209000;
define symbol m_boot_hdr_boot_data_start = 0x20209020;
define symbol m_boot_hdr_dcd_data_start = 0x20209030;

//place at address mem: m_interrupts_start { readonly section .intvec };
place at address mem: m_boot_hdr_conf_start { section .boot_hdr.conf };
place at address mem: m_boot_hdr_ivt_start { section .boot_hdr.ivt };
place at address mem: m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
place at address mem: m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };

keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };

SPDHOST scripts:

sdphost.exe -u 0x1fc9,0x0130 -- write-file 0x20208000 ivt_builtin_flashloader.bin
sdphost.exe -u 0x1fc9,0x0130 -- jump-address 0x20209000

Thanks.

-James

View solution in original post

JamesNgo · ‎09-28-2023

Hi Pavel,

To continue pursuing the solution I mentioned above, I need to generate the ivt_flashloader.bin (?!) that is for the SDPHOST to write to 0x202A000 (and jump to 0x2020A400) to execute. And after this, flashloader will execute. Please help review my simple steps below to see if there's anything missing/wrong:

Now, IAR generates the flashloader.srec as shown below:

I'm using imx-dtcm-unsigned.bd

Use ELFTOSB to generate the final BIN with the following command:

elftosb.exe -f imx -V -c imx-dtcm-unsigned.bd -o ivt_flashloader.bin flashloader.srec‍‍‍‍‍‍‍‍‍

Here's the problem:

thanks

JamesNgo · ‎09-29-2023