need help: ls1043 DDR tuning

[Hmc510]

soc:ls1043a

DDR:MT40A2G8VA-062E:B ,  x5, 4for 8GB,1 for ECC.

I use CW get a config files:

I tried two files to generate img

They all have problems running at BL2:

to use (0-2GB) DDR Data appears incorrect: (write ≠ read)

How should I solve it? Thanks

[khushbur]

Hi @Hmc510 

Can you please perform below validation with QCVS DDR tool.

1. Centering The Clock

2. Read ODT and Driver

3. Write ODT and Driver

Thanks

Khushbu

[Hmc510]

Hi

I unexpectedly solved this problem.CPU has been adjusted from 1.6G to 1.2G,the uboot startup.

I don't know why. SYSCLK & DDRCLK is 100M.

[Hmc510]

Yes, they all seem to have turned out very successful.

And I removed ECC(U20 & R146) chip from the board.Close ECC and regenerate configuration parameters; Still down in BL2.

And I tried the following CW configuration:

4GB: 1G8、8GB: 2G8.They all tested CW normally,hang up at BL2.

[khushbur]

Hi @Hmc510 

Can you please share boot logs in txt format.

Thanks

Khushbu

[Hmc510]

This is the startup log with ECC.

I tried to turn off OPTEE,It will also stop at BL2.

[Hmc510]

about MT40A2G8VA-062E:B I found a total of two documents online:

16gb_ddr4_x4x8_2cs_twindie.pdf  MICT_S_A0010972464_1-2574446.pdf

[Hmc510]

DDR PCB:

P05-DDR4.pdf

DDR 2G8 datasheet  MT40A2G8VA-062E:B:

MICT_S_A0010972464_1-2574446.pdf

Information supplement：

I modified the ATF code to test the DDR:

write data to 1K memory and then read back for verification. two messages were found:

1. Some bits have changed
2. CW read back data appears to be correct and ATF crc notify NG...(I'm sure there's no dizziness)

[Hmc510]

and CW test 0~2G is good :

[Hmc510]

@khushbur  This is where I obtain.CW test 0-2GB passed,The 0-2G test in BL2 is incorrect.

I also read back the DDRC register,They all have no problem.