Our product has four DDR4 chips on board. The type of DDR is MT40A512M16LY-062 IT:E, and the following is my configuration.
static const struct rc_timing rce[] = {
{1600, 8, 7},
{1867, 8, 7},
{2134, 8, 9},
{}
};
static const struct board_timing udimm[] = {
{0x04, rce, 0x01020304, 0x06070805},
};
struct dimm_params ddr_raw_timing = {
.n_ranks = 1,
.rank_density = 2147483648u,
.capacity = 2147483648u,
.primary_sdram_width = 32,
.ec_sdram_width = 16,
.n_row_addr = 15,
.n_col_addr = 10,
.bank_group_bits = 2,
.burst_lengths_bitmask = 0x0c,
.tckmin_x_ps = 938,
.tckmax_ps = 1500,
.caslat_x = 0x015FFC00,
.taa_ps = 13500,
.trcd_ps = 13500,
.trp_ps = 13500,
.tras_ps = 33000,
.trc_ps = 46500,
.twr_ps = 15000,
.trfc1_ps = 260000,
.trfc2_ps = 160000,
.trfc4_ps = 110000,
.tfaw_ps = 21000,
.trrds_ps = 3700,
.trrdl_ps = 5300,
.tccdl_ps = 5355,
.refresh_rate_ps = 7800000,
.dq_mapping[0] = 0x16,
.dq_mapping[1] = 0x36,
.dq_mapping[2] = 0x16,
.dq_mapping[3] = 0x36,
.dq_mapping[4] = 0x16,
.dq_mapping[5] = 0x36,
.dq_mapping[6] = 0x16,
.dq_mapping[7] = 0x36,
.dq_mapping[8] = 0x16,
.dq_mapping[9] = 0x0,
.dq_mapping[10] = 0x0,
.dq_mapping[11] = 0x0,
.dq_mapping[12] = 0x0,
.dq_mapping[13] = 0x0,
.dq_mapping[14] = 0x0,
.dq_mapping[15] = 0x0,
.dq_mapping[16] = 0x0,
.dq_mapping[17] = 0x0,
.dq_mapping_ors = 0,
.rc = 0x04,
};
NOTICE: 2 GB DDR4, 32-bit, CL=15, ECC off
INFO: Time used by DDR driver 780 ms
NOTICE: BL2: v1.5(debug):v21.02.0-rc3-33-ga75928d125-dirty
NOTICE: BL2: Built : 21:46:45, Jun 27 2021
INFO: Configuring TrustZone Controller
INFO: Value of region base = ffe00000
INFO: Value of region base = 1ffe00000
INFO: Value of region base = fbe00000
INFO: BL2: Doing platform setup
INFO: BL2: Loading image id 3
INFO: sd-mmc read done.
