dpmac17 sgmii Problems

[muaxi8]

lx2160a custom board。

Using SERDES1 Protocol: 1 (0x1)
Using SERDES2 Protocol: 7 (0x7)
Using SERDES3 Protocol: 3 (0x3)

Now I am using dpMAC17 SGMII of SerDES2 as the debugging network port. The PHY chip is AR0833. Using MII command under uboot, I can see that the PHY is in link state, but ping my host is not working.。

RCW parameter EC1_PMUX[833-832] is changed to 0x01,  but the ping still fails

[yipingwang]

Would you please provide your u-boot console log and the results of the following commands?

=> mdio list
FSL_MDIO0:
0 - Cortina CS4223 <--> DPMAC2@xlaui4
1 - AR8035 <--> DPMAC17@rgmii-id
2 - AR8035 <--> DPMAC18@rgmii-id
4 - Aquantia AQR107 <--> DPMAC3@xgmii
5 - Aquantia AQR107 <--> DPMAC4@xgmii
FSL_MDIO1:
0 - Inphi in112525_S03P <--> DPMAC6@25g-aui

=> mdio read DPMAC17@rgmii-id 1
Reading from bus FSL_MDIO0
PHY at address 1:
1 - 0x7949
=>

Is your PHY chip AR8033? Have you enabled the following in configs/lx2160ardb_tfa_defconfig

CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y

[muaxi8]

=> ping 10.0.1.119
Using DPMAC17@sgmii device

ARP Retry count exceeded; starting again
ping failed; host 10.0.1.119 is not alive

yes my  PHY chip is AR8033。

i have enabled the following in configs/lx2160ardb_tfa_defconfig

[yipingwang]

In board/freescale/lx2160a/eth_lx2160ardb.c, please modify the following section according to your custom board.

for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC18; i++) {
          interface = wriop_get_enet_if(i);
          switch (interface) {
          case PHY_INTERFACE_MODE_RGMII:
          case PHY_INTERFACE_MODE_RGMII_ID:
                           dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
                            wriop_set_mdio(i, dev);
                            break;
          default:
                          break;
}

Modify to:

for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC18; i++) {
          interface = wriop_get_enet_if(i);
          switch (interface) {
          case PHY_INTERFACE_MODE_SGMII:
                           dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
                            wriop_set_mdio(i, dev);
                            break;
          default:
                          break;
}

[muaxi8]

Yes, we have modified this part code , The problem remains。Does the DPC need to be modified?  We have checked the content of the DPC and there seems to be no problem

[yipingwang]

You could use mdio read command to check the status of a SGMII link.

=> mdio list
FSL_MDIO0:
4 - AR8031/AR8033 <--> DPMAC17@sgmii
FSL_MDIO1:
=> mdio read DPMAC17@sgmii 1
Reading from bus FSL_MDIO0
PHY at address 4:
1 - 0x7969
=>

The link partner link status bit is in Register #1 on the PHY. The 'Link Status' bit is bit #2 (from the left) of the last nibble. In your above result, the nibble of interest is "9" (d = b'1001'), and therefore the 'Link Status' = 0, which means 'link download'. If the link is up,  this bit would be a "1," and we would see 0x796d. 

So on your custom board the SGMII link status is download, please check the probable hardware issue.

[muaxi8]

The second read was link.

[yipingwang]

Few clarifications:

1. Do ping works on MAC18?
2. Few strange observation in U-boot log:

      (a). Clock configuration shown in uboot is not as per the selected protocol.

      (b). PCA: failed to select proper channel

MAC17 and MAC18 is same so same issue should be with MAC 18.

3. Can you share share schematic?

[muaxi8]

1. Do ping works on MAC18?

Re:

Dpmac18 (EC2) cannot be tested because it is not connected to any PHY.We only used mac17, our SERDES2's SGMII17 was connected to the AR8033, and our EC1 was connected to the KSZ9896 switch chip via RGMII.I think this might be a problem, so I'm just going to debug SGMII and leave RGMII alone for now

(a). Clock configuration shown in uboot is not as per the selected protocol.

Re: The clock configuration is printed directly in the source code, we did not remove, serdes2 clock is actually 161.xxxMhz.

(b). PCA: failed to select proper channel

Re: Our custom board is not using PCA9547 (I2C MUX, level 1), so there is this error。

 schematic:

链接：https://pan.baidu.com/s/14edfW8yig7c-qZyYTLk7xQ
提取码：2345

[yipingwang]

What is the status of link status between MAC and PHY?

You can check this as detail below:

On U-boot prompt:

printenv elf_load
elf_load=dcache off; tftp 0x80300000 <location of mdio>/mdio.bin; dcache on;
run elf_load 
go 0x80300000 read 0x8c47000 3 {0x8c47000: MAC 17 Base address}

a valid PCS link ix 0x00000004
bit 2 set

Please let us know .

[muaxi8]

I followed your prompts and programmed mdio.bin to 0x80300000, then read the MAC 17 Base address and got some values.

=> md 0x8c47000 4
08c47000: 00010200 00000000 00000810 00000000 ................
=>

I looked at the manual "LX2160ADPAA2RM. PDF "and did not see the register about the MAC link status

[yipingwang]

Please read using below command

go 0x80300000

read 0x8c47000 3

[muaxi8]

the usage is a little wrong. One parameter missing?

=> go 0x80300000 read 0x8c47000 3
## Starting application at 0x80300000 ...
Example expects ABI version 9
Actual U-Boot ABI version 9
Internal MDIO read / write
argc = 4
operation = "read"
mac offset = "0x8c47000"
dev addr = "3"
Usage: go 0x80300000 <read|write> <mac offset> <mmd> <reg> [data]

## Application terminated, rc = 0x0

——------------------------------------------------------------------------------------

=> go 0x80300000 read 0x8c47000 3 0
## Starting application at 0x80300000 ...
Example expects ABI version 9
Actual U-Boot ABI version 9
Internal MDIO read / write
argc = 5
operation = "read"
mac offset = "0x8c47000"
dev addr = "3"
reg addr = "0"
mdio_cfg bsy set
mdio_data bsy set

output data: 0x00000000

## Application terminated, rc = 0x0

[yipingwang]

Sorry for typo, correct command is

go 0x80300000 read 0x8c0b000 3 1

[muaxi8]

MAC and PHY link status is not ok? We are using SGMII, DPL or DPC need configuration ?

=> go 0x80300000 read 0x8c0b000 3 1
## Starting application at 0x80300000 ...
Example expects ABI version 9
Actual U-Boot ABI version 9
Internal MDIO read / write
argc = 5
operation = "read"
mac offset = "0x8c0b000"
dev addr = "3"
reg addr = "1"
mdio_cfg bsy set
mdio_data bsy set

output data: 0x00000000

## Application terminated, rc = 0x0
=> go 0x80300000 read 0x8c47000 3 1
## Starting application at 0x80300000 ...
Example expects ABI version 9
Actual U-Boot ABI version 9
Internal MDIO read / write
argc = 5
operation = "read"
mac offset = "0x8c47000"
dev addr = "3"
reg addr = "1"
mdio_cfg bsy set
mdio_data bsy set

output data: 0x00000000

## Application terminated, rc = 0x0

[yipingwang]

Thanks for update. Can you please view more registers to check if read is working correctly?

Please refer register details in LX2160ARM Rev0 07/2020 section 26.9.2 SGMII Registers (Please read register 0,2,3 also)

[muaxi8]

A little problem

=> mdio list
FSL_MDIO0:
4 - AR8031/AR8033 <--> DPMAC17@sgmii
FSL_MDIO1:
=> mdio read DPMAC17@sgmii 1
Reading from bus FSL_MDIO0
PHY at address 4:
1 - 0x796d
=> go 0x80300000 read 0x8c0b000 3 2
## Starting application at 0x80300000 ...
Example expects ABI version 9
Actual U-Boot ABI version 9
Internal MDIO read / write
argc = 5
operation = "read"
mac offset = "0x8c0b000"
dev addr = "3"
reg addr = "2"
mdio_cfg bsy set
mdio_data bsy set

output data: 0x00000000

## Application terminated, rc = 0x0
=> go 0x80300000 read 0x8c0b000 3 3
## Starting application at 0x80300000 ...
Example expects ABI version 9
Actual U-Boot ABI version 9
Internal MDIO read / write
argc = 5
operation = "read"
mac offset = "0x8c0b000"
dev addr = "3"
reg addr = "3"
mdio_cfg bsy set
mdio_data bsy set

output data: 0x00000000

## Application terminated, rc = 0x0
=> go 0x80300000 read 0x8c0b000 3 0
## Starting application at 0x80300000 ...
Example expects ABI version 9
Actual U-Boot ABI version 9
Internal MDIO read / write
argc = 5
operation = "read"
mac offset = "0x8c0b000"
dev addr = "3"
reg addr = "0"
mdio_cfg bsy set
mdio_data bsy set

output data: 0x00000000

## Application terminated, rc = 0x0

[yipingwang]

Please refer "Table 51 MAC Capabilities" This table shows different MAC address and there capability.

I understand customer is using MAC 17 hence to reading all the register customer needs to use address "8C4_7000h"

Syntax for Clause 45: (Please read status register multiple times)

go 0x80300000 read <mac address> <MMD device> <register>    

go 0x80300000 read 0x8c0b000 3 1  

0x8c0b000= MAC address

3->  Device: PCS address  (Table 287. Device Address Overview)

1-> PCS status register

Syntax for Clause 22: (Please read status register multiple times)

read <mac_addr> <mmd always 0>  <reg addr>  <any value: e.g. 0 this is a switch that tells its clause 22>

For example to read control register

go 0x80300000 read 0x8c47000 0 0 0

To Read status register

go 0x80300000 read 0x8c47000 0 1 0

Do customer is able to boot linux on board?

does ping don't work on Linux?

Can you detail about your setup?

Please use MAC17 address "8C4_7000" instead of 0x8c0b000.

[muaxi8]

Dear Yiping,

Could you help give a demo for mac loopback code in u-boot.

Such as mac17 mac loopback. Many thanks.

 

[yipingwang]

1. Please first update your mc firmware (attached)
As per the boot log your mc firmware version is "version: 10.24.0"

2. Please share dump of PHY register 5 (partner ability) using MDIO command on uboot

3. what is the clock frequency of CLK_SD2_F_P/N ?

[muaxi8]

hi yipingWang

1:

crc32+
fsl-mc: Booting Management Complex ... SUCCESS
fsl-mc: Management Complex booted (version: 10.24.0, boot status: 0x1)
Hit any key to stop autoboot: 0

2：

=> mdio list
FSL_MDIO0:
4 - AR8031/AR8033 <--> DPMAC17@sgmii
FSL_MDIO1:
=> mii read 4 5
CDE1
=> mii read 4 5
CDE1
=> mii dump
5. (cde1) -- Autonegotiation partner abilities register --
(8000:8000) 5.15 = 1 next page able
(4000:4000) 5.14 = 1 acknowledge
(2000:0000) 5.13 = 0 remote fault
(1000:0000) 5.12 = 0 (reserved)
(0800:0800) 5.11 = 1 asymmetric pause able
(0400:0400) 5.10 = 1 pause able
(0200:0000) 5. 9 = 0 100BASE-T4 able
(0100:0100) 5. 8 = 1 100BASE-X full duplex able
(0080:0080) 5. 7 = 1 100BASE-TX able
(0040:0040) 5. 6 = 1 10BASE-T full duplex able
(0020:0020) 5. 5 = 1 10BASE-T able
(001f:0001) 5. 4- 0 = 1 partner selector = IEEE 802.3 CSMA/CD

3：

CLK_SD2_F_P/N is 100Mhz

can you provide a demo of dpmac17 sgmii disable auto-negotiation ？