Wasn't this possibility canceled? I'm confused. According to LS1043A Reference Manual Rev. 3 02/2017 the DDR_SDRAM_CFG[DBW] has only one allowed (not reserved) value: 01b - 32-bit bus is used. Moreover, in the same Reference Manual a DDR bus width is specified as 32/36 bit, 16-bit not mentioned. The 16-bit width was maybe specified in some older Reference Manual, but I'm not sure, I cannot find the older document anymore.
Please, can you clarify this topic with respect to the current LS1043A Reference Manual (Rev. 3 02/2017)?
The destributor's support engenier told me:
Design team confirmed that rev 3 manual was corrected by mistake. I already mentioned required setup for 16-bit bus mode. For more information you can either use rev 1 or rev 2 LS1043A manuals, or LS1020A ref manual (all 16-bit instances in the DDR chapter are applicable to the LS1043A).