U-BOOT LS1043ARDB NAND

[carlos-m-ribeiro]

Good morning,

If we program the ls1043ardb u-boot for NAND (starting from ls1043ardb_nand_defconfig) in our custom board (with our ddr parameters), the boot stops but using the same ddr files for QSPI u-boot, the boot continues without problems.

Log for NAND:

U-Boot SPL 2020.04-dirty (Jul 16 2021 - 17:00:13 +0100)
Error, wrong i2c adapter 0 max 0 possible
Error, wrong i2c adapter 0 max 0 possible
Initialzing DDR using fixed setting
Configuring DDR for 1600 MT/s data rate

Best regards

[carlos-m-ribeiro]

And after we add in ddr.c and ddr.h the CONFIG_SYS_DDR_RAW_TIMING define, the log is:

U-Boot SPL 2020.04-dirty (Jul 20 2021 - 12:06:49 +0100)
Error, wrong i2c adapter 0 max 0 possible
Error, wrong i2c adapter 0 max 0 possible
Initializing DDR....

Thank you

[yipingwang]

The DDR controller initialization parameters defined in board/freescale/ls1043ardb/ddr.h in u-boot source code is only used for LS1043ARDB demo board, you need to use QCVS DDRv tool to calculate, optimize and validate DDR controller configuration parameters for your custom board.

Did you define ddr_raw_timing in board/freescale/ls1043ardb/ddr.c according to your DDR datasheet? 

If yes, you could try the following method to create a QCVS DDR project to connect to the target board to do optimization and validation.

1. Please define CONFIG_SYS_DDR_RAW_TIMING in include/configs/ls1043ardb.h and rebuild u-boot. Then boot u-boot image on your custom board.

2. In CodeWarrior IDE, please create a QCVS DDR project, in "DDR configuration" panel, please select "From target" Configuration mode, after type CodeWarrior TAP IP address, please click "Read from target", then create the QCVS DDR project with parameters read from your custom board.

3. Please complete DDRv Centering the clock, Read/Write ODT and driver validation and Operation DDR tests.

4. Please click Project->Generate Processor Expert Code, please refer to DDR controller configuration parameters in file uboot_ddr1.c in Generated_Code folder to configure DDR parameters in board/freescale/ls1043ardb/ddr.h in u-boot source code.

I attached QCVS DDRv tool user manual.

[carlos-m-ribeiro]

Thank you for your advise, now the DDR is ok, but we cannot boot from NAND again:

U-Boot 2020.04-dirty (Jul 21 2021 - 10:33:05 +0100)

SoC: LS1023A Rev1.1 (0x87920911)
Clock Configuration:
CPU0(A53):1000 MHz CPU1(A53):1000 MHz
Bus: 300 MHz DDR: 1600 MT/s FMAN: 600 MHz
Reset Configuration Word (RCW):
00000000: 0610000a 0c000000 00000000 00000000
00000010: 34550002 00004012 e0106000 c1002000
00000020: 00000000 00000000 00000000 0003cffc
00000030: 20004101 04102501 00000096 00000001
Model: LS1043A QDS Board
***********************************************
*** BOARD: AT16sxg, ALTICE LABS 2021 ***
***********************************************
BOOTING FROM...DRAM: Detected UDIMM Fixed DDR on board
3.9 GiB (DDR4, 32-bit, CL=11, ECC off)
Using SERDES1 Protocol: 13397 (0x3455)
SEC Firmware: config-1: no such config
SEC Firmware: error (-2)
SEC Firmware: Failed to load image
Waking secondary cores to start from fbd28000
All (2) cores are up.
Flash: "Error" handler, esr 0xbf000002
elr: 0000000082001990 lr : 0000000082078974 (reloc)
elr: 00000000fbd29990 lr : 00000000fbda0974
x0 : 00000000008eb0a0 x1 : 00000000000f4240
x2 : 00000000fbc22a88 x3 : 0000000000000000
x4 : 0000000000000000 x5 : 00000000fbc22a6c
x6 : 00000000000000f0 x7 : 0000000000000000
x8 : 0000000060000000 x9 : 000000000000000c
x10: 00000000fbde9eb8 x11: 00000000fbdaddda
x12: 000000000000000d x13: 000000000000d7e8
x14: 00000000fbc22a48 x15: 00000000ffffffff
x16: 0000000000000001 x17: 000000000000010f
x18: 00000000fbc25dc0 x19: 00000000008eb0b9
x20: 0000000000000001 x21: 0000000000989680
x22: 00000000fbde9eb8 x23: 000000001000a883
x24: 0000000000000000 x25: 00000000fbdaa884
x26: 000000001000c000 x27: 000000001001ae10
x28: 00000000fbc22b30 x29: 00000000fbc22a40

Code: d53be000 d65f03c0 d5033fdf d53be020 (b9015640)
Resetting CPU ...

[yipingwang]

If the NAND flash on your custom board is different from LS1043ARDB, you need to modify IFC controller configuration parameters according to the NAND flash on your custom board.

Please modify "NAND Flash Definitions" section in include/configs/ls1043ardb.h.

Please refer to https://community.nxp.com/t5/Layerscape-Knowledge-Base/IFC-Controller-Configuration-on-QorIQ-Custom-... for details.