TWR-LS1021A

[lizboxy]

正准备使用LS1021,并参考SPF-28673_C1 Demo,有几个问题想请教下:

1、 LS1020的时钟，哪些是必须的，哪些是可选的？

2、 供电芯片MC34VR500V7ES，选择LS1020+DDR4的情况，3.3V供电和Serdes供电会因为电压域原因导致不能同时上电，是否OK？
3、 SPF-28673_C1评估板上在MC34VR500V7ES输出部分使用了2颗INA220AIDGST输出电流/电压/功率监控器，是必须的吗？
4、 SPF-28673_C1评估板上在LS1020A的MAC部分又输入了一路125M时钟，这个是必须的吗？
5、 Serdes有2路时钟，他们与Serdes数据lane对应关系如何？是必须都给的吗？

请帮忙解答下,感谢!

[ufedor]

Please pose the questions in English.

[lizboxy]

Our customer is using LS1021 and check the reference design of the Demo TWR-LS1021A, SPF-28673_C1

1、 For the clock of LS1020,which must be needed and which one is Optional?

2、 For PMIC MC34VR5100，if as power for LS1020+DDR4,  support for both 3.3V and Serdes  is ok or not due to the 2different domain power which can not powered at the same time?
3、 In the SPF-28673_C1, 2pcs INA220AIDGST used as monitor of Voltage and Current at output of MC34VR500V7ES，so INA220 must be needed？
4、 In the SPF-28673_C1, another 125M clock is used for MAC of LS1021A, tt's necessary？
5、 For the 2clock for Serders ，how about the relationship about the Serdes' LANS? It's necessary？

[ufedor]

1) Please refer to the QorIQ LS1021A Reference Manual, 4.4.7 Clocking to select a clocking mode.

2) The question is not clear.

3) Usage of INA220 is not a must.

4) External 125 MHz reference clock (ECn_GTX_CLK125) is needed if RGMII interface is used.

5) Please refer to the QorIQ LS1021A Reference Manual, Table 33-2. Supported SerDes options, column "Per lane PLL mapping":

"1" corresponds to the PLL1

"2" corresponds to the PLL2

Example:

SRDS_PRTCL_S1 = 0x10

Per lane PLL mapping: 1211

Lanes A, C, D - PLL1

Lane B - PLL2

If PLLn is not used then it has to be powered down and corresponding reference clock is not needed.