The reason we have TBI registers mentioned in the initialization steps (for MII, RMII and RGMM) is because the elastic FIFO reset logic is actually included in the internal TBI Phy logic. Hence a reset of the TBI Phy was added to the eTSEC/dTSEC recommended initialization sequence to ensure no "garbage" data would reside in the elastic FIFO during the controller's initialization.
We will add additional note in the next RM release to clarify this.
For eTSEC1 the TBIPA value should be non-zero and distinct from external PHYs addresses (if any).
For eTSEC2 and eTSEC3 the TBIPA value can be any in range 1-31.
Note that TBI PHY registers have to be accessed by means of MDIO registers belonging to the configured eTSEC.
For eTSEC2 MDIO range starts at 2D6_4000 address offset
For eTSEC3 MDIO range starts at 2DA_4000 address offset