SD Clock source is not correct in LS1046

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SD Clock source is not correct in LS1046

Senior Contributor I

Hi NXP Team

My platform follow the LS1046ardb demo board.

I try to test  "boot form SD card", but I can not boot form SD.

(1) In Demo board The CLK1 = 156Mhz


(2) In my design board CLK1 =100Mhz


Why the CLK1 is different, my source code the same with Demoboard.

Do you have any advice?

The CLK1 is not correct.  I can not boot up form SD, right?

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NXP TechSupport
NXP TechSupport

Please refer to the following in checkboard function in board/freescale/ls1046ardb/ls1046ardb.c in u-boot source code.

int checkboard(void)
static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};


puts("SERDES Reference Clocks:\n");
sd1refclk_sel = CPLD_READ(sd1refclk_sel);
printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);

return 0;

The value of sd1refclk_sel is read from CPLD, however you didn't program CPLD firmware on your target board, so the variable sd1refclk_sel is 0, SD1_CLK1( freq[sd1refclk_sel]) is freq[0], it is 100MHZ.

So, please program CPLD and FPGA on your custom board.

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