Hello everybody,
I am trying to send cores 1, 2 and 3 (all are ARM A53) of the LS1043A in the power management state named PH20.
On the QorIQ LS1043A Reference Manual, Rev. 6, 07/2020
NXP has written a procedure that allows the cores to enter the PH20 state. I report as the procedure is described in the datasheet:
1. Set CPUECTLR [2: 0] CPU
retention control to a non-zero
value. Refer Arm® Cortex®-A53
Technical Reference Manual for
more information.
2. Set CPUECTLR [6] SMPEN to
1.The cluster power
management controller uses the
state of this bit to decide whether
to put the core into retention
(equals to one) or
powerdown (equals to zero).
3. Write to generic timer control
register SYS_Counter_CNTCR
to enable the Arm counter
CNTVALUEB [63: 0].
4. (IS THE SAME OF n ° 3 STEP)
Write to generic timer control
register SYS_Counter_CNTCR
to enable the Arm counter
CNTVALUEB [63: 0]
5. Set the RETREQn bit of
corresponding core in
SCFG_RETREQCR register for
RETENTION_REQ_EN at
arm_cluster to be set.
6. Set the PC_PH20_REQ bit in
RCPM_PCPH20SETR register
through Software.
7. Execute WFI Instruction of the
Core.
8. COP sends RETENTION_REQ
and waits for RETENTION
output from the core.
9. When RETENTION signal is
asserted at COP boundary, Core
state machine moves to PH20
been.
10. RCPM_PCPH20SR register
corresponding bit should get set.
Points 3 and 4 are the same, is there a copy error or is a piece of the procedure missing?
In case it is possible to have the complete detailed procedure to get the cores into the POWER MANAGEMENT STATE called PH20.
