Layerscape DDR4 PCB design

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Layerscape DDR4 PCB design

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miha_at_work
Contributor III

Hello.

What does mean note in AN5097: "The clock signal trace from the memory controller to any given DDR4 chip should be longer than it's corresponding strobe trace lenghth"? Do I correct understood it's mean the CK signal must arrive from processor pins to corresponding DDR4 chip pins slightly later than corresponding DQS signal and CK trace lengths from processor to each memory chip must be longer than each corresponding DQS?

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ufedor
NXP TechSupport
NXP TechSupport

Your understanding is correct.