Layerscape DDR4 PCB design

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Layerscape DDR4 PCB design

714 Views
miha_at_work
Contributor III

Hello.

What does mean note in AN5097: "The clock signal trace from the memory controller to any given DDR4 chip should be longer than it's corresponding strobe trace lenghth"? Do I correct understood it's mean the CK signal must arrive from processor pins to corresponding DDR4 chip pins slightly later than corresponding DQS signal and CK trace lengths from processor to each memory chip must be longer than each corresponding DQS?

Labels (1)
1 Reply

576 Views
ufedor
NXP Employee
NXP Employee

Your understanding is correct.