LX2160a: NOR flash sector protect

[csr202]

We have micron NOR flash mt25qu02g on lx2160a based custom design.
I'm using below command from u-boot to protect the data sector of the flash memory.
However, it seems flash protect is not working as, I'm able to erase flash memory even after protect command.

=> sf protect lock 0x500000 0x10000
=> sf erase 0x500000 0x10000
SF: 65536 bytes @ 0x500000 Erased: OK

Does current nxp_fspi/spi-nor driver has a support for ASP/Section protection for micron NOR flash mt25qu02g ?

Below is the status register for mt25q nor flash family. As per my initial investigation it has BP3 (bit6) and I don't see SR_BP3 bit is used in u-boot spi-nor driver. 

Please let me know your thoughts on this, thanks.

rsc202_0-1700199990277.png

[csr202]

It seems flash protection doesn't work on LX2160ARDB either. I've verified using "protect" and "sf protect" commands from u-boot (U-Boot 2019.04-gce862bb2d), but it doesn't seem to be working as expected. 

Please let me know if I'm missing any other configuration here?

[yipingwang]

I verified this function in 2023.04 u-boot provided in NXP latest released LSDK, it worked.

NOTICE: BL2: v2.8(release):android-13.0.0_2.0.0-rc1-1-g99195a23d-dirty
NOTICE: BL2: Built : 06:14:17, Jun 2 2023
NOTICE: UDIMM 18ADF2G72AZ-3G2E1
NOTICE: DDR4 UDIMM with 2-rank 64-bit bus (x8)

NOTICE: 32 GB DDR4, 64-bit, CL=22, ECC on, 256B, CS0+CS1
NOTICE: BL2: Booting BL31
NOTICE: BL31: v2.8(release):android-13.0.0_2.0.0-rc1-1-g99195a23d-dirty
NOTICE: BL31: Built : 06:14:17, Jun 2 2023
NOTICE: Welcome to lx2160ardb BL31 Phase

U-Boot 2023.04+fsl+g1e5b6c6bf2 (Sep 05 2023 - 06:13:49 +0000)

SoC: LX2160ACE Rev2.0 (0x87360020)
Clock Configuration:
CPU0(A72):2200 MHz CPU1(A72):2200 MHz CPU2(A72):2200 MHz
CPU3(A72):2200 MHz CPU4(A72):2200 MHz CPU5(A72):2200 MHz
CPU6(A72):2200 MHz CPU7(A72):2200 MHz CPU8(A72):2200 MHz
CPU9(A72):2200 MHz CPU10(A72):2200 MHz CPU11(A72):2200 MHz
CPU12(A72):2200 MHz CPU13(A72):2200 MHz CPU14(A72):2200 MHz
CPU15(A72):2200 MHz
Bus: 750 MHz DDR: 3200 MT/s
Reset Configuration Word (RCW):
00000000: 5883833c 24580058 00000000 00000000
00000010: 00000000 0c010000 00000000 00000000
00000020: 390001a0 00002580 00000000 00000096
00000030: 00000000 00000000 00000000 00000000
00000040: 00000000 00000000 00000000 00000000
00000050: 00000000 00000000 00000000 00000000
00000060: 00000000 00000000 00027000 00000000
00000070: 08b30010 00150020
Model: NXP Layerscape LX2160ARDB Board
Board: LX2160ACE Rev2.0-RDB, Board version: C, boot from FlexSPI DEV#0
FPGA: v9.0
SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz
SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz
SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz
VID: Core voltage after adjustment is at 826 mV
DRAM: 31.9 GiB
DDR 31.9 GiB (DDR4, 64-bit, CL=22, ECC on)
DDR Controller Interleaving Mode: 256B
DDR Chip-Select Interleaving Mode: CS0+CS1
optee optee: OP-TEE api uid mismatch
QSFP: detected Fiberstore QSFP-SR4-40G s/n: G1804130068 mfgdt: 20/18/05
Using SERDES1 Protocol: 19 (0x13)
Using SERDES2 Protocol: 5 (0x5)
Using SERDES3 Protocol: 2 (0x2)
PCIe1: pcie@3400000 disabled
PCIe2: pcie@3500000 disabled
PCIe3: pcie@3600000 Root Complex: x1 gen1
PCIe4: pcie@3700000 disabled
PCIe5: pcie@3800000 Root Complex: x4 gen3
PCIe6: pcie@3900000 disabled
Core: 70 devices, 25 uclasses, devicetree: separate
WDT: Started watchdog@23a0000 with servicing every 1000ms (30s timeout)
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from SPIFlash... SF: Detected mt35xu512aba with page size 256 Bytes, erase size 128 KiB, total 64 MiB
*** Warning - bad CRC, using default environment

EEPROM: NXID v1
In: serial_pl01x
Out: serial_pl01x
Err: serial_pl01x
SEC0: RNG instantiated
Net: mdio@8b97000:0 is connected to DPMAC5@25g-aui. Reconnecting to DPMAC6@25g-aui
e1000: 00:15:17:be:d7:83
eth0: DPMAC2@xlaui4, eth1: DPMAC3@usxgmii, eth2: DPMAC4@usxgmii, eth3: DPMAC5@25g-aui, eth4: DPMAC6@25g-aui, eth5: DPMAC17@rgmii-id, eth6: DPMAC18@rgmii-id, eth7: e1000#0
SF: Detected mt35xu512aba with page size 256 Bytes, erase size 128 KiB, total 64 MiB
device 0 offset 0x640000, size 0x80000
SF: 524288 bytes @ 0x640000 Read: OK
device 0 offset 0xf00000, size 0x100000
SF: 1048576 bytes @ 0xf00000 Read: OK
device 0 offset 0xa00000, size 0x300000
SF: 3145728 bytes @ 0xa00000 Read: OK
device 0 offset 0xe00000, size 0x100000
SF: 1048576 bytes @ 0xe00000 Read: OK
crc32+ MC firmware version 10.37.0

fsl-mc: Booting Management Complex ... SUCCESS
fsl-mc: Management Complex booted (version: 10.37.0, boot status: 0x1)
Hit any key to stop autoboot: 0
=>
=>
=> sf protect lock 0x1000000 0x10000
=> sf erase 0x1000000 0x10000
SF: 65536 bytes @ 0x1000000 Erased: ERROR -22
=>