LX2160A Some Issues

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qingshanli
Contributor I

Hi, about LX2160A, I have some issues.

1.Some Power NC pins(For example P28,R27,U27 etc. and T2,V2,Y2 etc.) whether or not to connect to corresponding power VDD and GVDD?

2.SENSEVDD_PL/SENSEVDD_CA/SENSEVDD_CB and SENSEGND_PL/SENSEGND_CA/SENSEGND_CB need feed back to regulator sense input pins by some serial resistors. How to select the value of these resistors?
 

Catch97FD(06-17-16-45-02).jpg

3. Power sequence as follows, please help to check.
USB_HVDD(3.3V) -> VDD(0.85V)/OVDD(1.8V)/SD_OVDD(1.8V)/EVDD(1.8V)/ USB_SVDD(0.8V) -> SD_SVDD(0.92V)/SD3_SVDD(0.92V)/AVDD(0.9V) -> GVDD(1.2V)/VTT(0.6V)
 
4. Whether SD_SVDD and SD3_SVDD need to be adjusted to 0.92V?
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yipingwang
NXP TechSupport
NXP TechSupport

1.Some Power NC pins(For example P28,R27,U27 etc. and T2,V2,Y2 etc.) whether or not to connect to corresponding power VDD and GVDD?
Refer Table

2. Pinout list by bus of datasheet of LX2160A.
Note for NC pins, 'Do not connect. These pins should be left floating.'

3. Power sequence as follows, please help to check.
USB_HVDD(3.3V) -> VDD(0.85V)/OVDD(1.8V)/SD_OVDD(1.8V)/EVDD(1.8V)/ USB_SVDD(0.8V) -> SD_SVDD(0.92V)/SD3_SVDD(0.92V)/AVDD(0.9V) -> GVDD(1.2V)/VTT(0.6V)
Refer 3.3 Power sequencing In LX2160A datasheet
'All other power supplies (GnVDD, OVDD, EVDD, USB_HVDD, USB_SVDD, USB_SDVDD, SD_SVDD, SD_OVDD, TA_BB_VDD, TH_VDD, AVDD (cores,
platform, DDR), and AVDD_SDm_PLLn) have no ordering requirement with respect to one another and with respect to VDD. All supplies must be at their stable values within 400 ms.'

4. Whether SD_SVDD and SD3_SVDD need to be adjusted to 0.92V?
Recommended operating values of SD_SVDD and SD3_SVDD
SD_SVDD -- 0.9 V - 30 mV to 0.9 V + 50 mV V -
SD3_SVDD 0.9 V - 30 mV to 0.9 V + 50 mV V

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yipingwang
NXP TechSupport
NXP TechSupport

1.Some Power NC pins(For example P28,R27,U27 etc. and T2,V2,Y2 etc.) whether or not to connect to corresponding power VDD and GVDD?
Refer Table

2. Pinout list by bus of datasheet of LX2160A.
Note for NC pins, 'Do not connect. These pins should be left floating.'

3. Power sequence as follows, please help to check.
USB_HVDD(3.3V) -> VDD(0.85V)/OVDD(1.8V)/SD_OVDD(1.8V)/EVDD(1.8V)/ USB_SVDD(0.8V) -> SD_SVDD(0.92V)/SD3_SVDD(0.92V)/AVDD(0.9V) -> GVDD(1.2V)/VTT(0.6V)
Refer 3.3 Power sequencing In LX2160A datasheet
'All other power supplies (GnVDD, OVDD, EVDD, USB_HVDD, USB_SVDD, USB_SDVDD, SD_SVDD, SD_OVDD, TA_BB_VDD, TH_VDD, AVDD (cores,
platform, DDR), and AVDD_SDm_PLLn) have no ordering requirement with respect to one another and with respect to VDD. All supplies must be at their stable values within 400 ms.'

4. Whether SD_SVDD and SD3_SVDD need to be adjusted to 0.92V?
Recommended operating values of SD_SVDD and SD3_SVDD
SD_SVDD -- 0.9 V - 30 mV to 0.9 V + 50 mV V -
SD3_SVDD 0.9 V - 30 mV to 0.9 V + 50 mV V

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qingshanli
Contributor I
2.SENSEVDD_PL/SENSEVDD_CA/SENSEVDD_CB and SENSEGND_PL/SENSEGND_CA/SENSEGND_CB need feed back to regulator sense input pins by some serial resistors. How to select the value of these resistors?
 
qingshanli_0-1656054382654.jpeg

 

 

 

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yipingwang
NXP TechSupport
NXP TechSupport

2.SENSEVDD_PL/SENSEVDD_CA/SENSEVDD_CB and SENSEGND_PL/SENSEGND_CA/SENSEGND_CB need feed back to regulator sense input pins by some serial resistors. How to select the value of these resistors?
[NXP]: Refer section 4.6 Ganged sense-line implementation example in AN5407_Rev2

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