LX2160A DDRV error PHY exceeded 128

[guignbt2v]

Hi all,

On a custom LX2160A board we currently have the following DDRV error result while running the 'centering the clock' test:

#################### Result for: ddr_vref_searcher ###### Run 1 ###################################

Test result: [
Test input parameters exception: PHY exceeded 128!
]

Would someone know how to have an idea of the reason why we have this result? For instance how to enable more logs, run some ccs command from the ccs shell and get more info?

Thanks

[kenli]

ddrv 128 error usually  shows a hardware issue here 

including DDR-related voltage levels or layout margin issues.your design must be strictly followed docs as khushbur mentioned.

[guignbt2v]

Hi,

Thanks for your messages, we didn't give up !

You were right, our problem was length matching related. We solved this hardware part: DDR now properly initializes and we manage to run DDRV tests.
However we notice that we cannot easily increase DDR speed. Using the nice 'Diag margin stage' tests, at 1900MTs we have the following Read (top) / Write Margin diags (below) :

The 'eyes' seem pretty open, don't they?
The write margin eyes seem somehow strange but look similar to the DDRV exemples we found in your documentation.

However the 'normal' (older) 'Margin stage' tests behave slightly differently: 'Read Margin' passes, but the 'Write margin' fails, everything remains 'yellow', no 'green'. What it the difference between these tests and what could explain this behaviour?

Furthermore when we try to inscrease speed, 2000MTs, we can notice that we get almost only 1D PHY errors. Which parameter in our configuration could explain such a steep performance reduction?

Thanks for your help

[kenli]

Based on past experience, if downgrading DDR frequency can solve the issue but increasing frequency cannot, it indicates that the signal integrity (SI) requirements are not being met. Therefore, it is recommended to perform SI simulation to further investigate the issue.

[guignbt2v]

Hello Khushbu,

FYI we noticed a length mismatch in part of the DDR control signals. Schematics is/seems correct but this length mismatch could explain our current problem as a small part of the AN DDR constrains isn't respected.
We should be able to fix this precise problem around mid June.

Thanks,

Guillaume

[guignbt2v]

Hi again Khushbu

So... I first did the "open the panel from Window->Show View->Console" part and then the DDRV again.
As it was somehow difficult to do a copy/paste of the logs I attached a screenshot of the CodeWarrior windows once DDRV done.

I tried with both QCVS version 4.22 and the latest 4.24 version.

FYI in the 'CodeWarrior Connection Server' window (and shell) I could enable the log using the command 'log verb' (with an optional filename) and here I have a LOT of logs...

Any idea how to progress using DDRVs? To answer your (past/future) question regarding hardware design we already knew the AN5407 and AN5097 documents you kindly refered to. So as far as I know our design respects recommanded design rules. We either have a software problem (really wrong DDR configuration) or a hardware problem. Would you have an idea how we can progress to understand why we get this DDRV result?

Thanks,

G.

[khushbur]

Hi @guignbt2v 

Please make sure that you have correct RCW loaded on the board

Is it possible to share a schematic here and your ddr configuration for further debugging.

Thanks

Khushbu

[guignbt2v]

Hi Khushbu,

For now the RCW is a 'minimal' RCW without Serdes, just enough to use SYSCLK, to boot, to display uart logs and to try using DDR. This minimal RCW config works fine on the LX2160ARDB: starts booting, uart logs, DDR ok. With our board (same SYSCLK frequency, same RCW) : starts booting, uart logs, DDR PHY (1D error), reason why we went to DDRVs. With DDR PHY DEBUG enabled we get a 'PMU: Error: dbyte 0 lane 0 failed read deskew', and FYI the very same error on a board without DDR4 device...

Not sure I could share here our schematics. We would perhap need to switch to a 'support ticket'.
Currently waiting for an internal feedback about it.

Thanks,

G.

[guignbt2v]

Hi Khushbu,
Thanks for your answers. Just back from vacation .Going to send you logs ASAP this week.
G.

[guignbt2v]

Hi Khuhbu,

Thanks for your message. Sorry, I am not sure I know how to send you 'console logs'.

I already put in my first message the content of the 'test_optimized_clock_centering_segm_C_0_0_.log' file, only file generated by the DDRV run (along with the 'script file').

Otherwise I can send ou a screenshot of the DDRV results, easy to describe anyway: very first test, in the 'Auto search and detect DDR VREF start value', red, and fail reason 'PHY exceeded 128!'.

I could also send you the DDRV project, or send CCS related logs. You can even propose me some CCS commands if you want to.

Thanks,

G.

[khushbur]

Hi @guignbt2v 

Please check your hardware design with AN5407 - Layerscape LX2160A and LX2162A Design Checklist, and AN5097 - Hardware and Layout Design Considerations for DDR4 SDRAM.

Please open the panel from Window->Show View->Console to get a logs

Thanks

Khushbu

[khushbur]

Hi @guignbt2v 

Can you please share a console logs in detail.

Thanks

Khushbu