LS1046A Remote PCI-E Loopback Enable

[barrybarge]

I am trying to loopback a PCI-E peripheral that supports remote loopback to verify operation of the PCI-E bus via the Code Warrior QCVS SERDES verification tool and its BIST test.  How would I initiate this loopback from the CPU (I assume through registers access or code)?

[barrybarge]

In another community message(https://community.nxp.com/t5/Layerscape/PCIe-loopback-test/m-p/1052827), the person indicates "I got a sequence of commands that we have to execute to create a loopback from RC".  This is what I need to use the BIST function in QCVS -  the commands to put the endpoint in remote loopback.

[barrybarge]

By using the BIST scenario, is this supposed to put the far end in loopback without any additional commands?  Assuming you mean External Loopback, this does not work, no apparent loopback is created, so the test fails.

[Oswalag]

Create PCIe loopback between RC and EP's
To enable loopback, set bit '2' on the register at offset 0x710. Ensure read/modify write, as register has other fields that should not be modified.
See the value of this register from our system in lab, it may differ on your board.
[0x03400710] 00070124
Once this bit is set, LTSSM status will show 'LOOPBACK'

Please take a look in the RM chapter 25.5.1.18 PEX PF0 Debug register (PEX_PF0_DBG)

in 25.5.1.18.4 Fields you can find more information about the Link Training Status State Machine (LTSSM) status

[barrybarge]

If I read the 0x710 offset given, the values are all 0's, which indicate to me that I am not accessing the right register to do the loopback.  For background, the link is on PEX3, so per the RM, the base address PEX3_LUT is 368_0000h.  If I dump the PEX_PF0_DBG register (0x36c_07fc)  per 25.5.1.18, I get the following value:

0x00000011 Which corresponds to LTSSM of POLL_COMPLIANCE

I dumped both 0x368_0710 and 0x36c_0710 and get all zeros.

I have written to bit '2' at both locations and the LTSSM does not change, and reading back the address still results in all 0's.

Is it possible this is not the correct register offset for the LS1046A?  I assume this is not a documented register and bit defintions.

[Oswalag]

You are not able to see 0x710 register under pcie configuration register map because it is a hidden register, please try the following commands used in a test with two LS1046ARDB board connected back to back using PCIe Adaptor card on SLOT2.

Please try Boot both the board to Uboot prompt and issue command at prompt 

Commands to Execute:

@rc

mw 3500710 00010124

@ EP

mw 1eb0874 30

after this try run the BIST test. In case that the configuration doesn't work please open a technical case to provide more information.

[Oswalag]

Hello,

Please go to QCVS SerDes Tool User Guide and follow the steps for a BIST scenario in chapter:

1.3.3.1 BIST scenario